Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 45
CPM Electrical Characteristics
14.2 IDMA Controller AC Electrical Specifications
Table 17 provides the IDMA controller timings as shown in Figure 41 through Figure 44.
Figure 41. IDMA External Requests Timing Diagram
Table 17. IDMA Controller Timing
Num Characteristic
All Frequencies
Unit
Min Max
40 DREQ
setup time to clock high 7 — ns
41 DREQ
hold time from clock high
1
1
Applies to high-to-low mode (EDM = 1).
3—ns
42 SDACK
assertion delay from clock high — 12 ns
43 SDACK
negation delay from clock low — 12 ns
44 SDACK
negation delay from TA low — 20 ns
45 SDACK
negation delay from clock high — 15 ns
46 TA
assertion to rising edge of the clock setup time (applies to external TA)7 —ns
41
40
DREQ
(Input)
CLKO
(Output)