Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 49
CPM Electrical Characteristics
Table 21 provides the NMSI internal clock timing.
107 RXD3 hold time from RCLK3 rising edge
2
5.00 — ns
108 CD3
setup Time to RCLK3 rising edge 5.00 — ns
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1.
2
Also applies to CD and CTS hold time when they are used as an external sync signal.
Table 21. NMSI Internal Clock Timing
Num Characteristic
All Frequencies
Unit
Min Max
100 RCLK3 and TCLK3 frequency
1
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 3/1.
0.00 SYNCCLK/3 MHz
102 RCLK3 and TCLK3 rise/fall time — — ns
103 TXD3 active delay (from TCLK3 falling edge) 0.00 30.00 ns
104 RTS3
active/inactive delay (from TCLK3 falling edge) 0.00 30.00 ns
105 CTS3
setup time to TCLK3 rising edge 40.00 — ns
106 RXD3 setup time to RCLK3 rising edge 40.00 — ns
107 RXD3 hold time from RCLK3 rising edge
2
2
Also applies to CD and CTS hold time when they are used as an external sync signals.
0.00 — ns
108 CD3
setup time to RCLK3 rising edge 40.00 — ns
Table 20. NMSI External Clock Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max