Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
54 Freescale Semiconductor
CPM Electrical Characteristics
14.7 SPI Master AC Electrical Specifications
Table 23 provides the SPI master timings as shown in Figure 55 and Figure 56.
Figure 55. SPI Master (CP = 0) Timing Diagram
Table 23. SPI Master Timing
Num Characteristic
All Frequencies
Unit
Min Max
160 MASTER cycle time 4 1024 t
cyc
161 MASTER clock (SCK) high or low time 2 512 t
cyc
162 MASTER data setup time (inputs) 15 — ns
163 Master data hold time (inputs) 0 — ns
164 Master data valid (after SCK edge) — 10 ns
165 Master data hold time (outputs) 0 — ns
166 Rise time output — 15 ns
167 Fall time output — 15 ns
SPIMOSI
(Output)
SPICLK
(CI = 0)
(Output)
SPICLK
(CI = 1)
(Output)
SPIMISO
(Input)
162
Data
166167161
161 160
msb lsb msb
msb Data lsb msb
167 166
163
166
167
165 164