Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor 57

FEC Electrical Characteristics

15 FEC Electrical Characteristics

This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the

timing specifications for the MII signals are independent of system clock frequency (part speed

designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or

3.3 V.

15.1 MII Receive Signal Timing (MII_RXD[3:0], MII_RX_DV, MII_RX_ER,

MII_RX_CLK)

The receiver functions correctly up to a MII_RX_CLK maximum frequency of 25MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed the

MII_RX_CLK frequency –1%.

Table 25 provides information on the MII receive signal timing.

Figure 59 shows MII receive signal timing.

Figure 59. MII Receive Signal Timing Diagram

15.2 MII Transmit Signal Timing (MII_TXD[3:0], MII_TX_EN,

MII_TX_ER, MII_TX_CLK)

The transmitter functions correctly up to a MII_TX_CLK maximum frequency of 25 MHz + 1%. There is

no minimum frequency requirement. In addition, the processor clock frequency must exceed the

MII_TX_CLK frequency – 1%.

Table 25. MII Receive Signal Timing

Num Characteristic Min Max Unit

M1 MII_RXD[3:0], MII_RX_DV, MII_RX_ER to MII_RX_CLK setup 5 — ns

M2 MII_RX_CLK to MII_RXD[3:0], MII_RX_DV, MII_RX_ER hold 5 — ns

M3 MII_RX_CLK pulse width high 35% 65% MII_RX_CLK period

M4 MII_RX_CLK pulse width low 35% 65% MII_RX_CLK period

MII_RX_CLK (Input)

MII_RXD[3:0] (Inputs)

MII_RX_DV

MII_RX_ER