Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
58 Freescale Semiconductor
FEC Electrical Characteristics
Table 26 provides information about the MII transmit signal timing,.
Figure 60 shows the MII transmit signal timing diagram.
Figure 60. MII Transmit Signal Timing Diagram
15.3 MII Async Inputs Signal Timing (MII_CRS, MII_COL)
Table 27 provides information about the MII async inputs signal timing.
Figure 61 shows the MII asynchronous inputs signal timing diagram.
Figure 61. MII Async Inputs Timing Diagram
Table 26. MII Transmit Signal Timing
Num Characteristic Min Max Unit
M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns
M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 —
M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period
M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period
Table 27. MII Async Inputs Signal Timing
Num Characteristic Min Max Unit
M9 MII_CRS, MII_COL minimum pulse width 1.5 — MII_TX_CLK period
MII_TX_CLK (Input)
MII_TXD[3:0] (Outputs)
MII_TX_EN
MII_TX_ER
M5
M7
M8
M6
MII_CRS, MII_COL
M9