Datasheet
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
76 Freescale Semiconductor
Document Revision History
17 Document Revision History
Table 32 lists significant changes between revisions of this document.
Table 32. Document Revision History
Revision Date Changes
4 • Updated template.
• On page 1, updated first paragraph and added a second paragraph.
• After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 2) and
renumbered the rest of the figures.
•In Table 9, for reset timings B29f and B29g added footnote indicating that the formula only applies
to bus operation up to 50 MHz.
•In Figure 4, changed all reference voltage measurement points from 0.2 and 0.8 V to 50% level.
•In Ta bl e 1 7, changed num 46 description to read, “TA
assertion to rising edge ...”
•In Figure 42, changed TA
to reflect the rising edge of the clock.
3.1 1/18/2005 Document template update.
3.0 11/2004 • Added sentence to Spec B1A about EXTCLK and CLKOUT being in Alignment for Integer Values
• Added a footnote to Spec 41 specifying that EDM = 1
• Broke the Section 16.1, “Pin Assignments,” into 2 smaller sections for the JEDEC and non-JEDEC
pinouts.
2.0 12/2003 Put 852T on the 1st page in place of 8245.
Figure 62 on page 59 had overbars added on signals CR (pin G2) and WAIT_A (pin P4).
1.8 7/2003 Changed the pinout to be JEDEC Compliant, changed timing parameters B28a through B28d, and
B29d to show that TRLX can be 0 or 1.
1.7 5/2003 Changed the SPI Master Timing Specs. 162 and 164
1.6 4/2003 Changed the package drawing in Figure 15-63
1.5 4/2003 Changed 5 Port C pins with interrupt capability to 7 Port C pins. Added the Note: solder sphere
composition for MPC852TVR and MPC852TCVR devices is 95.5%Sn 45%Ag 0.5%Cu to Figure
15-63
1.4 2/2003 Changed Table 15-30 Pin Assignments for the PLL Pins V
SSSYN1
, V
SSSYN
, V
DDSYN
1.3 1/2003 Added subscripts to timing diagrams for B1-B35, to specify memory controller settings for the specific
edges.
1.2 1/2003 In Table 15-30, specified EXTCLK as 3.3 V.
1.1 12/2002 Added fast Ethernet controller to the features
1 11/2002 Added values for 80 and 100 MHz
0 10/2002 Initial release