Freescale Semiconductor Document Number: MPC852TEC Rev. 4, 09/2007 Technical Data MPC852T PowerQUICC™ Hardware Specifications This document contains detailed information for the MPC852T power considerations, DC/AC electrical characteristics, AC timing specifications, and pertinent electrical and physical characteristics. For information about functional characteristics of the processor, refer to the MPC866 PowerQUICC™ Family Reference Manual (MPC866UM).
Overview 1 Overview The MPC852T is a 0.18-micron derivative of the MPC860 PowerQUICC™ family, and can operate up to 100 MHz on the MPC8xx core with a 66-MHz external bus. The MPC852T has a 1.8-V core and a 3.3-V I/O operation with 5-V TTL compatibility. The MPC852T integrated communications controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications.
Features • • • • • — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller-programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbytes–256 Mbytes) — Selectable write protection — On-chip bus arbitration logic Fast Ethernet controller (FEC)
Features • • • • • • • • Two baud rate generators — Independent (can be connected toany SCC3/4 or SMC1) — Allows changes during operation — Autobaud support option Two SCCs (serial communication controllers) — Ethernet/IEEE 802.
Features 4-Kbyte Instruction Instruction Cache Bus Embedded MPC8xx Processor Core System Interface Unit (SIU) Unified Bus Instruction MMU 32-Entry ITLB Load/Store Bus Memory Controller External Internal Bus Interface Bus Interface Unit Unit 4-Kbyte Data Cache System Functions Data MMU 32-Entry DTLB PCMCIA-ATA Interface Fast Ethernet Controller DMAs FIFOs 10/100 Base-T Media Access Control Parallel I/O 2 Baud Rate Generators 2 Interrupt 8-Kbyte Timers Controllers Dual-Port RAM 32-Bit RISC Contro
Maximum Tolerated Ratings 3 Maximum Tolerated Ratings This section provides the maximum tolerated voltage and temperature ranges for the MPC852T. Table 1 provides the maximum ratings and operating temperatures. Table 1. Maximum Tolerated Ratings Rating Symbol Supply voltage1 Value Unit VDDL (core voltage) – 0.3 to 3.4 V VDDH (I/O voltage) – 0.3 to 4 V – 0.3 to 3.4 V 100 mV VDDSYN Difference between VDDL to VDDSYN Input voltage2 Vin GND – 0.
Thermal Characteristics Table 2. Operating Temperatures Rating Symbol Value Unit TA(min) 0 °C Tj(max) 95 °C TA(min) – 40 °C Tj(max) 100 °C Temperature 1 (standard) Temperature (extended) 1 Minimum temperatures are guaranteed as ambient temperature, TA. Maximum temperatures are guaranteed as junction temperature, Tj.
Power Dissipation 5 Power Dissipation Table 4 provides power dissipation information. The modes are 1:1, where CPU and bus speeds are equal, and 2:1 mode, where CPU frequency is twice bus speed. Table 4. Power Dissipation (PD) Die Revision Bus Mode Frequency (MHz) Typical1 Maximum2 Unit 50 110 140 mW 66 150 180 mW 66 140 160 mW 80 170 200 mW 100 210 250 mW 1:1 0 2:1 1 2 Typical power dissipation is measured at 1.9 V. Maximum power dissipation at VDDL and VDDSYN is at 1.9 V.
Thermal Calculation and Measurement Table 5. DC Electrical Specifications (continued) Characteristic Symbol Min Max Unit Input leakage current, Vin = 5.5 V (Except TMS, TRST, DSCK and DSDI pins) for 5-V tolerant pins 1 Iin — 100 µA Input leakage current, Vin = VDDH (Except TMS, TRST, DSCK, and DSDI) IIn — 10 µA Input leakage current, Vin = 0 V (Except TMS, TRST, DSCK and DSDI pins) IIn — 10 µA Input capacitance2 Cin — 20 pF Output high voltage, IOH = -2.0 mA, VDDH = 3.
Thermal Calculation and Measurement where: TA = ambient temperature (ºC) RθJA = package junction-to-ambient thermal resistance (ºC/W) PD = power dissipation in package The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated that errors of a factor of two (in the quantity TJ – TA) are possible. 7.
References If the board temperature is known and the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. For this method to work, the board and board mounting must be similar to the test board used to determine the junction-to-board thermal resistance, namely a 2s2p (board with a power and a ground plane) and vias attaching the thermal balls to the ground plane. 7.
Power Supply and Power Sequencing 9 Power Supply and Power Sequencing This section provides design considerations for the MPC852T power supply. The MPC852T has a core voltage (VDDL) and PLL voltage (VDDSYN) that operates at a lower voltage than the I/O voltage VDDH. The I/O section of the MPC852T is supplied with 3.3 V across VDDH and VSS (GND). The signals PA[0:3], PA[8:11], PB15, PB[24:25]; PB[28:31], PC[4:7], PC[12:13], PC15] PD[3:15], TDI, TDO, TCK, TRST, TMS, MII_TXEN, MII_MDIO are 5-V tolerant.
Layout Practices The MBMR[GPLB4DIS], PAPAR, PADIR, PBPAR, PBDIR, PCPAR, and PCDIR should be configured with the mandatory value in Table 6 in the boot code after the reset deasserts. Table 6.
Bus Signal Timing 12 Bus Signal Timing The maximum bus speed that the MPC852T supports is 66 MHz. Table 7 shows the frequency ranges for standard part frequencies. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) 50 MHz 66 MHz Part Frequency Min Max Min Max Core 40 50 40 66.67 Bus 40 50 40 66.67 Table 8.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B3 CLKOUT pulse width high (MIN = 0.4 × B1, MAX = 0.6 × B1) B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 × B1) 7.60 — 6.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B15 CLKOUT to TEA High-Z (MIN = 0.00 × B1 + 2.50) 2.50 15.00 2.50 15.00 2.50 15.00 2.50 15.00 ns B16 TA, BI valid to CLKOUT (setup time) (MIN = 0.00 × B1 + 6.00) 6.00 — 6.00 — 6.00 — 6.00 — ns B16a TEA, KR, RETRY, CR valid to CLKOUT (setup time) (MIN = 0.00 × B1 + 4.5) 4.50 — 4.50 — 4.50 — 4.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max 13.20 — 10.50 — 8.00 — 5.60 — ns — 9.00 9.00 ns B24a A(0:31) and BADDR(28:30) to CS asserted GPCM ACS = 11 TRLX = 0 (MIN = 0.50 × B1 – 2.00) B25 CLKOUT rising edge to OE, WE(0:3)/BS_B[0:3] asserted (MAX = 0.00 × B1 + 9.00) B26 CLKOUT rising edge to OE negated (MAX = 0.00 × B1 + 9.00) 2.00 9.00 2.00 9.00 2.00 9.00 2.00 9.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B29b CS negated to D(0:31), DP(0:3), High Z GPCM write access, ACS = 00, TRLX = 0,1 and CSNT = 0 (MIN = 0.25 × B1 – 2.00) 5.60 — 4.30 — 3.00 — 1.80 — ns B29c CS negated to D(0:31), DP(0:3) High-Z GPCM write access, TRLX = 0, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 (MIN = 0.50 × B1 – 2.00) 13.20 — 10.50 — 8.00 — 5.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B30b WE(0:3)/BS_B[0:3] negated to A(0:31) Invalid GPCM BADDR(28:30) invalid GPCM write access, TRLX = 1, CSNT = 1. CS negated to A(0:31) Invalid GPCM write access TRLX = 1, CSNT = 1, ACS = 10, or ACS == 11 EBDF = 0 (MIN = 1.50 × B1 – 2.00) 43.50 — 35.50 — 28.00 — 20.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B32a CLKOUT falling edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 (MAX = 0.25 × B1 + 6.80) 7.60 14.30 6.30 13.00 5.00 11.80 3.80 10.50 ns B32b CLKOUT rising edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MAX = 0.00 × B1 + 8.00) 1.50 8.00 1.
Bus Signal Timing Table 9. Bus Operation Timings (continued) 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid - as requested by control bit BST2 in the corresponding word in the UPM (MIN = 0.75 × B1 – 2.00) 20.70 — 16.70 — 13.00 — 9.40 — ns B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM (MIN = 0.25 × B1 – 2.00) 5.
Bus Signal Timing Figure 4 is the control timing diagram. CLKOUT A B Outputs A B Outputs D C Inputs D C Inputs A Maximum output delay specification. B Minimum output hold time. C Minimum input setup time specification. D Minimum input hold time specification. Figure 4. Control Timing Figure 5 provides the timing for the external clock. CLKOUT B1 B3 B1 B4 B2 B5 Figure 5. External Clock Timing MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 6 provides the timing for the synchronous output signals. CLKOUT B8 B7 B9 Output Signals B8a B7a B9 Output Signals B8b B7b Output Signals Figure 6. Synchronous Output Signals Timing Figure 7 provides the timing for the synchronous active pull-up and open-drain output signals. CLKOUT B13 B11 B12 TS, BB B13a B11a B12a TA, BI B14 B15 TEA Figure 7. Synchronous Active Pull-Up Resistor and Open-Drain Outputs Signals Timing MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 8 provides the timing for the synchronous input signals. CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 8. Synchronous Input Signals Timing Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the control of the UPM in the memory controller. CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 9. Input Data Timing in Normal Case MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.) CLKOUT TA B20 B21 D[0:31], DP[0:3] Figure 10. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1 Figure 11 through Figure 14 provide the timing for the external bus read that various GPCM factors control.
Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B24 B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure 12. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 10) CLKOUT B11 B12 TS B8 B22b A[0:31] B22c B23 CSx B24a B25 B26 OE B18 B19 D[0:31], DP[0:3] Figure 13. External Bus Read Timing (GPCM Controlled—TRLX = 0, ACS = 11) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing CLKOUT B11 B12 TS B8 A[0:31] B22a B23 CSx B27 OE B26 B27a B22b B22c B18 B19 D[0:31], DP[0:3] Figure 14. External Bus Read Timing (GPCM Controlled—TRLX = 0 or 1, ACS = 10, ACS = 11) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 15 through Figure 17 provide the timing for the external bus write that various GPCM factors control. CLKOUT B11 B12 TS B8 B30 A[0:31] B22 B23 CSx B25 B28 WE[0:3] B29b B26 OE B29 B8 B9 D[0:31], DP[0:3] Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing CLKOUT B11 B12 TS B30a B30c B8 A[0:31] B28b B28d B22 B23 CSx B29c B29g B25 WE[0:3] B29a B29f B26 OE B28a B28c B8 B9 D[0:31], DP[0:3] Figure 16. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing CLKOUT B11 B12 TS B8 B30b B30d A[0:31] B22 B28b B28d B23 CSx B25 B29e B29i WE[0:3] B29d B29h B26 OE B29b B8 B28a B28c B9 D[0:31], DP[0:3] Figure 17. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 1) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 18 provides the timing for the external bus that the UPM controls. CLKOUT B8 A[0:31] B31a B31d B31c B31b B31 CSx B34 B34a B34b B32a B32d B32c B32b B32 BS_A[0:3] B35 B36 B35a B33a B35b B33 GPL_A[0:5], GPL_B[0:5] Figure 18. External Bus Timing (UPM Controlled Signals) MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 19 provides the timing for the asynchronous asserted UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 19. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing Figure 20 provides the timing for the asynchronous negated UPWAIT signal that the UPM controls. CLKOUT B37 UPWAIT B38 CSx BS_A[0:3] GPL_A[0:5], GPL_B[0:5] Figure 20.
Bus Signal Timing Figure 21 provides the timing for the synchronous external master access that the GPCM controls. CLKOUT B41 B42 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx Figure 21. Synchronous External Master Access Timing (GPCM Handled ACS = 00) Figure 22 provides the timing for the asynchronous external master memory access that the GPCM controls. CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 22.
Bus Signal Timing Table 10 provides interrupt timing for the MPC852T. . Table 10. Interrupt Timing All Frequencies Characteristic1 Num Unit Min 1 Max I39 IRQx valid to CLKOUT rising edge (set up time) 6.00 ns I40 IRQx hold time after CLKOUT 2.00 ns I41 IRQx pulse width low 3.00 ns I42 IRQx pulse width high 3.
Bus Signal Timing Table 11 shows the PCMCIA timing for the MPC852T. Table 11. PCMCIA Timing 33 MHz Num 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max A(0:31), REG valid to PCMCIA Strobe asserted.1 (MIN = 0.75 × B1 – 2.00) 20.70 — 16.70 — 13.00 — 9.40 — ns J83 A(0:31), REG valid to ALE negation.1 (MIN = 1.00 × B1 – 2.00) 28.30 — 23.00 — 18.00 — 13.20 — ns J84 CLKOUT to REG valid (MAX = 0.25 × B1 + 8.00) 7.60 15.60 6.30 14.30 5.00 13.00 3.80 11.
Bus Signal Timing Figure 26 provides the PCMCIA access cycle timing for the external bus read. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 PCOE, IORD P52 ALE B18 B19 D[0:31] Figure 26. PCMCIA Access Cycles Timing External Bus Read MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Figure 27 provides the PCMCIA access cycle timing for the external bus write. CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 B8 B9 P54 PCWE, IOWR P52 ALE D[0:31] Figure 27. PCMCIA Access Cycles Timing External Bus Write Figure 28 provides the PCMCIA WAIT signals detection timing. CLKOUT P55 P56 WAITA Figure 28. PCMCIA WAIT Signals Detection Timing MPC852T PowerQUICC™ Hardware Specifications, Rev.
Bus Signal Timing Table 12 shows the PCMCIA port timing for the MPC852T. Table 12. PCMCIA Port Timing 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max — 19.00 — 19.00 — 19.00 — 19.00 ns J95 CLKOUT to OPx Valid (MAX = 0.00 × B1 + 19.00) J96 HRESET negated to OPx drive1 (MIN = 0.75 × B1 + 3.00) 25.70 — 21.70 — 18.00 — 14.40 — ns J97 IP_Xx valid to CLKOUT rising edge (MIN = 0.00 × B1 + 5.00) 5.00 — 5.00 — 5.00 — 5.
Bus Signal Timing Table 13 shows the debug port timing for the MPC852T. Table 13. Debug Port Timing All Frequencies Num Characteristic Unit Min Max 3 × TCLOCKOUT — — J82 DSCK cycle time J83 DSCK clock pulse width 1.25 × TCLOCKOUT — — J84 DSCK rise and fall times 0.00 3.00 ns J85 DSDI input data setup time 8.00 — ns J86 DSDI data hold time 5.00 — ns J87 DSCK low to DSDO data valid 0.00 15.00 ns J88 DSCK low to DSDO invalid 0.00 2.
Bus Signal Timing Table 14 shows the reset timing for the MPC852T. Table 14. Reset Timing 33 MHz Num 40 MHz 50 MHz 66 MHz Characteristic Unit Min Max Min Max Min Max Min Max J82 CLKOUT to HRESET high impedance (MAX = 0.00 × B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns J83 CLKOUT to SRESET high impedance (MAX = 0.00 × B1 + 20.00) — 20.00 — 20.00 — 20.00 — 20.00 ns J84 RSTCONF pulse width (MIN = 17.00 × B1) 515.20 — 425.00 — 340.00 — 257.
Bus Signal Timing Figure 33 shows the reset timing for the data bus configuration. HRESET R71 R76 RSTCONF R73 R74 R75 D[0:31] (IN) Figure 33. Reset Timing—Configuration from Data Bus Figure 34 provides the reset timing for the data bus weak drive during configuration. CLKOUT R69 HRESET R79 RSTCONF R77 R78 D[0:31] (OUT) (Weak) Figure 34. Reset Timing—Data Bus Weak Drive During Configuration MPC852T PowerQUICC™ Hardware Specifications, Rev.
IEEE 1149.1 Electrical Specifications Figure 35 provides the reset timing for the debug port configuration. CLKOUT R70 R82 SRESET R80 R80 R81 R81 DSCK, DSDI Figure 35. Reset Timing—Debug Port Configuration 13 IEEE 1149.1 Electrical Specifications Table 15 provides the JTAG timings for the MPC852T shown in Figure 36 through Figure 39. Table 15. JTAG Timing All Frequencies Num Characteristic Unit Min Max J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.
IEEE 1149.1 Electrical Specifications TCK J82 J83 J82 J83 J84 J84 Figure 36. JTAG Test Clock Input Timing TCK J85 J86 TMS, TDI J87 J88 J89 TDO Figure 37. JTAG Test Access Port Timing Diagram TCK J91 J90 TRST Figure 38. JTAG TRST Timing Diagram TCK J92 J94 Output Signals J93 Output Signals J95 J96 Output Signals Figure 39. Boundary Scan (JTAG) Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev.
CPM Electrical Characteristics 14 CPM Electrical Characteristics This section provides the AC and DC electrical specifications for the communications processor module (CPM) of the MPC852T. 14.1 Port C Interrupt AC Electrical Specifications Table 16 provides the timings for port C interrupts. Table 16. Port C Interrupt Timing 33.
CPM Electrical Characteristics 14.2 IDMA Controller AC Electrical Specifications Table 17 provides the IDMA controller timings as shown in Figure 41 through Figure 44. Table 17.
CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 43 DATA 46 TA (Input) SDACK Figure 42. SDACK Timing Diagram—Peripheral Write, Externally-Generated TA CLKO (Output) TS (Output) R/W (Output) 42 44 DATA TA (Output) SDACK Figure 43. SDACK Timing Diagram—Peripheral Write, Internally-Generated TA MPC852T PowerQUICC™ Hardware Specifications, Rev.
CPM Electrical Characteristics CLKO (Output) TS (Output) R/W (Output) 42 45 DATA TA (Output) SDACK Figure 44. SDACK Timing Diagram—Peripheral Read, Internally-Generated TA 14.3 Baud Rate Generator AC Electrical Specifications Table 18 provides the baud rate generator timings as shown in Figure 45. Table 18.
CPM Electrical Characteristics 14.4 Timer AC Electrical Specifications Table 19 provides the general-purpose timer timings as shown in Figure 46. Table 19. Timer Timing All Frequencies Num Characteristic Unit Min Max 61 TIN/TGATE rise and fall time 10 — ns 62 TIN/TGATE low time 1 — clk 63 TIN/TGATE high time 2 — clk 64 TIN/TGATE cycle time 3 — clk 65 CLKO low to TOUT valid 3 25 ns CLKO 60 61 63 62 TIN/TGATE (Input) 61 64 65 TOUT (Output) Figure 46.
CPM Electrical Characteristics Table 20. NMSI External Clock Timing (continued) All Frequencies Num 1 2 Characteristic Unit Min Max 107 RXD3 hold time from RCLK3 rising edge2 5.00 — ns 108 CD3 setup Time to RCLK3 rising edge 5.00 — ns The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater than or equal to 2.25/1. Also applies to CD and CTS hold time when they are used as an external sync signal. Table 21 provides the NMSI internal clock timing. Table 21.
CPM Electrical Characteristics Figure 47 through Figure 49 show the NMSI timings. RCLK3 102 102 101 106 100 RxD3 (Input) 107 108 CD3 (Input) 107 CD3 (SYNC Input) Figure 47. SCC NMSI Receive Timing Diagram TCLK3 102 102 101 100 TxD3 (Output) 103 105 RTS3 (Output) 104 104 CTS3 (Input) 107 CTS3 (SYNC Input) Figure 48. SCC NMSI Transmit Timing Diagram MPC852T PowerQUICC™ Hardware Specifications, Rev.
CPM Electrical Characteristics TCLK3 102 102 101 100 TxD3 (Output) 103 RTS3 (Output) 104 107 104 105 CTS3 (Echo Input) Figure 49. HDLC Bus Timing Diagram 14.6 Ethernet Electrical Specifications Table 22 provides the Ethernet timings as shown in Figure 50 through Figure 54. Table 22.
CPM Electrical Characteristics Table 22. Ethernet Timing (continued) All Frequencies Num 1 2 Characteristic Unit Min Max 135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns 136 RSTRT inactive delay (from TCLK3 falling edge) 10 50 ns 137 REJECT width low 1 — CLK 138 CLKO1 low to SDACK asserted 2 — 20 ns 139 CLKO1 low to SDACK negated 2 — 20 ns The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.
CPM Electrical Characteristics TCLK3 128 128 129 131 121 TxD3 (Output) 132 133 134 TENA(RTS3) (Input) RENA(CD3) (Input) (Note 2) Notes: 1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the CSL bit is set in the buffer descriptor at the end of the frame transmission. Figure 52. Ethernet Transmit Timing Diagram RCLK3 RxD3 (Input) 0 1 1 BIT1 Start Frame De- BIT2 136 125 RSTRT (Output) Figure 53.
CPM Electrical Characteristics 14.7 SPI Master AC Electrical Specifications Table 23 provides the SPI master timings as shown in Figure 55 and Figure 56. Table 23.
CPM Electrical Characteristics SPICLK (CI=0) (Output) 161 167 166 161 160 SPICLK (CI=1) (Output) 163 167 162 166 SPIMISO (Input) msb Data 165 lsb msb 164 167 SPIMOSI (Output) 166 msb Data lsb msb Figure 56. SPI Master (CP = 1) Timing Diagram 14.8 SPI Slave AC Electrical Specifications Table 24 provides the SPI slave timings as shown in Figure 57 and Figure 58. Table 24.
CPM Electrical Characteristics SPISEL (Input) 172 171 174 SPICLK (CI = 0) (Input) 173 182 173 181 170 SPICLK (CI = 1) (Input) 177 181 182 180 SPIMISO (Output) msb 178 Data 175 lsb msb 179 176 SPIMOSI (Input) Undef 181 182 msb Data lsb msb Figure 57.
FEC Electrical Characteristics 15 FEC Electrical Characteristics This section provides the AC electrical specifications for the fast Ethernet controller (FEC). Note that the timing specifications for the MII signals are independent of system clock frequency (part speed designation). Also, MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V. 15.
FEC Electrical Characteristics Table 26 provides information about the MII transmit signal timing,. Table 26. MII Transmit Signal Timing Num Characteristic Min Max Unit M5 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER invalid 5 — ns M6 MII_TX_CLK to MII_TXD[3:0], MII_TX_EN, MII_TX_ER valid — 25 — M7 MII_TX_CLK pulse width high 35% 65% MII_TX_CLK period M8 MII_TX_CLK pulse width low 35% 65% MII_TX_CLK period Figure 60 shows the MII transmit signal timing diagram.
FEC Electrical Characteristics 15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC) Table 28 provides information on the MII serial management channel signal timing. The FEC functions correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under investigation. Table 28.
Mechanical Data and Ordering Information 16 Mechanical Data and Ordering Information Table 29 identifies the packages and operating frequencies orderable for the MPC852T. Table 29. MPC852T Package/Frequency Orderable Package Type Plastic ball grid array (VR and ZT suffix) Plastic ball grid array (CVR and CZTsuffix) 16.
Mechanical Data and Ordering Information 16.1.1 JEDEC Compliant Pinout Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the MPC866 PowerQUICC™ Family Reference Manual. NOTE: This is the top view of the device.
Mechanical Data and Ordering Information Table 30 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 30. Pin Assignments—JEDEC Standard Name Pin Number Type A[0:31] B15, A15, A14, C14, D13, E11, B14, A13, C13, B13, D12, E10, C12, Bidirectional B12, A12, D11, E9, C11, A9, A11, D10, C10, B8, A10, D9, C9, C8, Three-state (3.3 V only) B11, A8, B10, B9, D8 TSIZ0, REG E8 Bidirectional Three-state (3.3 V only) TSIZ1 E7 Bidirectional Three-state (3.
Mechanical Data and Ordering Information Table 30. Pin Assignments—JEDEC Standard (continued) Name Pin Number Type FRZ IRQ6 H4 Bidirectional (3.3 V only) IRQ0 P13 Input (3.3 V only) IRQ1 M11 Input (3.3 V only) M_TX_CLK IRQ7 N12 Input (3.
Mechanical Data and Ordering Information Table 30. Pin Assignments—JEDEC Standard (continued) Name Pin Number Type EXTAL M1 Analog Input (1.8 V only) CLKOUT N6 Output EXTCLK N2 Input (1.8 V only) ALE_A H1 Output CE1_A E5 Output CE2_A B3 Output WAIT_A N3 Input (3.3 V only) IP_A0 T2 Input (3.3 V only) IP_A1 M6 Input (3.3 V only) IP_A2, IOIS16_A R3 Input (3.3 V only) IP_A3 M5 Input (3.3 V only) IP_A4 T3 Input (3.3 V only) IP_A5 N5 Input (3.
Mechanical Data and Ordering Information Table 30.
Mechanical Data and Ordering Information Table 30.
Mechanical Data and Ordering Information Table 30.
Mechanical Data and Ordering Information 16.1.2 The non-JEDEC Pinout Figure 64 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For additional information, see the PowerQUICC™ Family Reference Manual. NOTE: This figure shows the top view of the device.
Mechanical Data and Ordering Information Table 31 contains a list of the MPC852T input and output signals and shows multiplexing and pin assignments. Table 31. Pin Assignments—Non-JEDEC Name Pin Number Type A[0:31] C16, B16, B15, D15, E14, F12, C15, B14, D14, C14, E13, F11, D13, Bidirectional C13, B13, E12, F10, D12, B10, B12, E11, D11, C9, B11, E10, D10, Three-state (3.3 V only) D9, C12, B9, C11, C10, E9 TSIZ0, REG F9 Bidirectional Three-state (3.3 V only) TSIZ1 F8 Bidirectional Three-state (3.
Mechanical Data and Ordering Information Table 31. Pin Assignments—Non-JEDEC (continued) Name Pin Number Type BB G4 Bidirectional Active Pull-up (3.3 V only) FRZ, IRQ6 J5 Bidirectional (3.3 V only) IRQ0 R14 Input (3.3 V only) IRQ1 N12 Input (3.3 V only) IRQ7, M_TX_CLK P13 Input (3.
Mechanical Data and Ordering Information Table 31. Pin Assignments—Non-JEDEC (continued) Name Pin Number Type IP_A1 N7 Input (3.3 V only) IP_A2, IOIS16_A T4 Input (3.3 V only) IP_A3 N6 Input (3.3 V only) IP_A4 U4 Input (3.3 V only) IP_A5 P6 Input (3.3 V only) IP_A6 N8 Input (3.3 V only) IP_A7 T3 Input (3.3 V only) DSCK J3 Bidirectional Three-state (3.3 V only) IWP[0:1], VFLS[0:1] J4, H2 Bidirectional (3.3 V only) OP0 L2 Bidirectional (3.
Mechanical Data and Ordering Information Table 31.
Mechanical Data and Ordering Information Table 31.
Mechanical Data and Ordering Information Table 31.
Mechanical Data and Ordering Information 16.2 Mechanical Dimensions of the PBGA Package For more information on the printed-circuit board layout of the PBGA package, including thermal via design and suggested pad layout, refer to Plastic Ball Grid Array Application Note (order number: AN1231) that is available from your local Freescale sales office. Figure 65 shows the mechanical dimensions of the PBGA package. Notes: 1. All dimensions are in millimeters. 2.
Document Revision History 17 Document Revision History Table 32 lists significant changes between revisions of this document. Table 32. Document Revision History Revision Date 4 3.1 Changes • Updated template. • On page 1, updated first paragraph and added a second paragraph. • After Table 2, inserted a new figure showing the undershoot/overshoot voltage (Figure 2) and renumbered the rest of the figures.
Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev.
Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev.
Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC852T PowerQUICC™ Hardware Specifications, Rev.
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