Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
22 Freescale Semiconductor
Bus Signal Timing
Figure 4 is the control timing diagram.
Figure 4. Control Timing
Figure 5 provides the timing for the external clock.
Figure 5. External Clock Timing
CLKOUT
Outputs
A
B
Outputs
B
A
Inputs
D
C
Inputs
C
D
A Maximum output delay specification.
B Minimum output hold time.
C Minimum input setup time specification.
D Minimum input hold time specification.
CLKOUT
B1
B5
B3
B4
B1
B2