Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
24 Freescale Semiconductor
Bus Signal Timing
Figure 8 provides the timing for the synchronous input signals.
Figure 8. Synchronous Input Signals Timing
Figure 9 provides normal case timing for input data. It also applies to normal read accesses under the
control of the UPM in the memory controller.
Figure 9. Input Data Timing in Normal Case
CLKOUT
TA
, BI
TEA, KR,
RETRY
, CR
BB, BG, BR
B16
B17
B16a
B17a
B16b
B17
CLKOUT
TA
D[0:31],
DP[0:3]
B16
B17
B19
B18