Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 25
Bus Signal Timing
Figure 10 provides the timing for the input data controlled by the UPM for data beats where DLT3 = 1 in
the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Figure 10. Input Data Timing When Controlled by UPM in the Memory Controller and DLT3 = 1
Figure 11 through Figure 14 provide the timing for the external bus read that various GPCM factors
control.
Figure 11. External Bus Read Timing (GPCM Controlled—ACS = 00)
CLKOUT
TA
D[0:31],
DP[0:3]
B20
B21
CLKOUT
A[0:31]
CSx
OE
WE[0:3]
TS
D[0:31],
DP[0:3]
B11 B12
B23
B8
B22
B26
B19
B18
B25
B28