Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
28 Freescale Semiconductor
Bus Signal Timing
Figure 15 through Figure 17 provide the timing for the external bus write that various GPCM factors
control.
Figure 15. External Bus Write Timing (GPCM Controlled—TRLX = 0 or 1, CSNT = 0)
CLKOUT
A[0:31]
CSx
WE[0:3]
OE
TS
D[0:31],
DP[0:3]
B11
B8
B22 B23
B12
B30
B28B25
B26
B8 B9
B29
B29b