Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
34 Freescale Semiconductor
Bus Signal Timing
Table 10 provides interrupt timing for the MPC852T.
.
Figure 24 provides the interrupt detection timing for the external level-sensitive lines.
Figure 24. Interrupt Detection Timing for External Level Sensitive Lines
Figure 25 provides the interrupt detection timing for the external edge-sensitive lines.
Figure 25. Interrupt Detection Timing for External Edge Sensitive Lines
Table 10. Interrupt Timing
Num Characteristic
1
1
The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as
level-sensitive. The IRQ
lines are synchronized internally and need not be asserted or negated with reference to the CLKOUT.
The timings I41, I42, and I43 are specified to allow the correct function of the IRQ
lines detection circuitry, and have no direct
relation with the total system interrupt latency that the MPC852T is able to support.
All Frequencies
Unit
Min Max
I39 IRQ
x valid to CLKOUT rising edge (set up time) 6.00 ns
I40 IRQ
x hold time after CLKOUT 2.00 ns
I41 IRQ
x pulse width low 3.00 ns
I42 IRQ
x pulse width high 3.00 ns
I43 IRQ
x edge-to-edge time 4 × T
CLOCKOUT
—
CLKOUT
IRQ
x
I39
I40
CLKOUT
IRQ
x
I41 I42
I43
I43