Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 39
Bus Signal Timing
Table 13 shows the debug port timing for the MPC852T.
Figure 31 provides the input timing for the debug port clock.
Figure 31. Debug Port Clock Input Timing
Figure 32 provides the timing for the debug port.
Figure 32. Debug Port Timings
Table 13. Debug Port Timing
Num Characteristic
All Frequencies
Unit
Min Max
J82 DSCK cycle time 3 × T
CLOCKOUT
——
J83 DSCK clock pulse width 1.25 × T
CLOCKOUT
——
J84 DSCK rise and fall times 0.00 3.00 ns
J85 DSDI input data setup time 8.00 — ns
J86 DSDI data hold time 5.00 — ns
J87 DSCK low to DSDO data valid 0.00 15.00 ns
J88 DSCK low to DSDO invalid 0.00 2.00 ns
DSCK
D61
D61
D63
D62
D62
D63
DSCK
DSDI
DSDO
D64
D65
D66
D67