Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 51
CPM Electrical Characteristics
Figure 49. HDLC Bus Timing Diagram
14.6 Ethernet Electrical Specifications
Table 22 provides the Ethernet timings as shown in Figure 50 through Figure 54.
Table 22. Ethernet Timing
Num Characteristic
All Frequencies
Unit
Min Max
120 CLSN width high 40 — ns
121 RCLK3 rise/fall time — 15 ns
122 RCLK3 width low 40 — ns
123 RCLK3 clock period
1
80 120 ns
124 RXD3 setup time 20 — ns
125 RXD3 hold time 5 — ns
126 RENA active delay (from RCLK3 rising edge of the last data bit) 10 — ns
127 RENA width low 100 — ns
128 TCLK3 rise/fall time — 15 ns
129 TCLK3 width low 40 — ns
130 TCLK3 clock period
1
99 101 ns
131 TXD3 active delay (from TCLK3 rising edge) — 50 ns
132 TXD3 inactive delay (from TCLK3 rising edge) 6.5 50 ns
133 TENA active delay (from TCLK3 rising edge) 10 50 ns
134 TENA inactive delay (from TCLK3 rising edge) 10 50 ns
TCLK3
CTS3
(Echo Input)
102
100
104
TxD3
(Output)
102 101
RTS3
(Output)
103
104107
105