Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
52 Freescale Semiconductor
CPM Electrical Characteristics
Figure 50. Ethernet Collision Timing Diagram
Figure 51. Ethernet Receive Timing Diagram
135 RSTRT active delay (from TCLK3 falling edge) 10 50 ns
136 RSTRT
inactive delay (from TCLK3 falling edge) 10 50 ns
137 REJECT
width low 1 — CLK
138 CLKO1 low to SDACK
asserted
2
—20ns
139 CLKO1 low to SDACK
negated
2
—20ns
1
The ratios SyncCLK/RCLK3 and SyncCLK/TCLK3 must be greater or equal to 2/1.
2
SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Table 22. Ethernet Timing (continued)
Num Characteristic
All Frequencies
Unit
Min Max
CLSN(CTS1)
120
(Input)
RCLK3
121
RxD3
(Input)
121
RENA(CD3)
(Input)
125
124 123
127
126
Last Bit