Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 53
CPM Electrical Characteristics
Figure 52. Ethernet Transmit Timing Diagram
Figure 53. CAM Interface Receive Start Timing Diagram
Figure 54. CAM Interface REJECT
Timing Diagram
TCLK3
128
TxD3
(Output)
128
TENA(RTS3)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, the CSL bit is set in the
buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD3)
(Input)
133 134
132
131 121
129
(Note 2)
RCLK3
RxD3
(Input)
RSTRT
(Output)
0
136
125
1 1 BIT1 BIT2
Start Frame De-
REJECT
137