Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 59
FEC Electrical Characteristics
15.4 MII Serial Management Channel Timing (MII_MDIO, MII_MDC)
Table 28 provides information on the MII serial management channel signal timing. The FEC functions
correctly with a maximum MDC frequency in excess of 2.5 MHz. The exact upper bound is under
investigation.
Figure 62 shows the MII serial management channel timing diagram.
Figure 62. MII Serial Management Channel Timing Diagram
Table 28. MII Serial Management Channel Timing
Num Characteristic Min Max Unit
M10 MII_MDC falling edge to MII_MDIO output invalid (minimum propagation
delay)
0— ns
M11 MII_MDC falling edge to MII_MDIO output valid (max prop delay) — 25 ns
M12 MII_MDIO (input) to MII_MDC rising edge setup 10 — ns
M13 MII_MDIO (input) to MII_MDC rising edge hold 0 — ns
M14 MII_MDC pulse width high 40% 60% MII_MDC period
M15 MII_MDC pulse width low 40% 60% MII_MDC period
M11
MII_MDC (Output)
MII_MDIO (Output)
M12
M13
MII_MDIO (Input)
M10
M14
MM15