Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Freescale Semiconductor 61
Mechanical Data and Ordering Information
16.1.1 JEDEC Compliant Pinout
Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface. For additional
information, see the MPC866 PowerQUICC™ Family Reference Manual.
NOTE: This is the top view of the device.
Figure 63. Pinout of PBGA Package—JEDEC Standard
N/C
WR
VDDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 VDDL A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0
CE2_A GPL_A3 WE3
GPL_A0
GPL_A4
CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI
CS2 OE
MII_CRS BS_A3 A22 A30
WE0 BS_A1 A24
TS
TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29VDDL
A
B
C
D
E
MII_COL
BB
VFLS_1 RSV BURST
DSCK
VFLS_0
AS BADDR30
OP1
OP2
BADDR29 BADDR28
VDDL
XTAL EXTCLK WAIT_A
PORST VDDSYN VSSSYN1
PC12 PA11
TMS TRST
VDDL MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
VDDL PA0
PD12 PD14
N/C PD11
GND
K
L
VDDH
M
N
VDDL
IP_A7
IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 VDDL D18 D3 D1 D4 D8 MII_TXEN
P
R
T
D30
12
34567 8
91011
12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
VDDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1