Datasheet

MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
68 Freescale Semiconductor
Mechanical Data and Ordering Information
16.1.2 The non-JEDEC Pinout
Figure 64 shows the non-JEDEC pinout of the PBGA package as viewed from the top surface. For
additional information, see the PowerQUICC™ Family Reference Manual.
NOTE: This figure shows the top view of the device.
Figure 64. Pinout of PBGA Package—Non-JEDEC
N/C
WR
V
DDL
BDIP
BR
CR
ALE_A
KR
OP0
OP3
EXTAL
N/C
CS7 GPL_A2 WE2 BS_A0 V
DDL
A28 A18 A23 A19 A14 A7 A2 A1 N/C
CS0
CE2_A GPL_A3 WE3
GPL_A0
GPL_A4
CS3 CS5 WE1 BS_A2 A26 A25 A21 A17 A12 A8 A3 N/C
BI
CS2 OE
MII_CRS BS_A3 A22 A30
WE0 BS_A1 A24
TS
TEA
A29A27A13A9A6A0N/C
A20A15A10A4N/CPB29V
DDL
B
C
D
E
MII_COL
BB
VFLS_1 RSV BURST
DSCK
VFLS_0
AS BADDR30
OP1
OP2
BADDR29 BADDR28
V
DDL
XTAL EXTCLK WAIT_A
PORST V
DDSYN
VSSSYN1
PC12 PA11
TMS TRST
V
DDL
MDIO
PA10 PB24
G
H
J
F
PA8 PA9
PC6 PA3
PA1 PB15
V
DDL
PA0
PD12 PD14
N/C PD11
GND
K
L
V
DDH
M
N
V
DDL
IP_A7
IP_A2 PD10 N/CD31
IP_A0 IP_A4 DP2
D6 D19 D5 D2 D27 D13 D0 PD5
PD7 N/C
D28
D7 D22 V
DDL
D18D3D1D4D8MII_TXEN
P
R
T
D30
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
GPL_A5
TA
BG
HRESET
RSTCONF
V
DDL
N/C
VSSSYN
DP0
DP3
IP_A5 D25 D21 D15 D10 D17 IRQ7 PD6 PD9CLKOUT
D29 D24 D20 D16 D11 D12 IRQ0 PD4DP1
PB31 PC13
PB30 TDO
PB28 TDI
TCK PB25
PC5 PC7
PD13 PA2
N/C PC4
PD8 PD15
A31CS6
PC15
D23
SRESET
FRZ
CE_1A CS4 TSIZ1 A16 A11 A5 N/CTSIZ0
IP_A3 IP_A6 D26 D14 D9 IRQ1 PD3IP_A1
CS1
U
17