Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Functional diagram
- 6. Pinning information
- 7. Limiting values
- 8. Recommended operating conditions
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Package outline
- 12. Abbreviations
- 13. Revision history
- 14. Legal information
- 15. Contact information
- 16. Contents

1. General description
The NPIC6C595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset input (MR
). A LOW on MR resets both the shift register and
storage register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The
data in the shift register is transferred to the storage register on a LOW-to-HIGH transition
of the STCP input and to the Q7S output on a LOW-to-HIGH transition of the SHCP input.
If both clocks are connected together, the shift register is always one clock pulse ahead of
the storage register. Data in the storage register drives the gate of the output
extended-drain NMOS transistor whenever the output enable input (OE
) is LOW. A HIGH
on OE
causes the outputs to assume a high-impedance OFF-state. Operation of the OE
input does not affect the state of the registers. The open-drain outputs are 33 V/100 mA
continuous current extended-drain NMOS transistors designed for use in systems that
require moderate load power such as LEDs. Integrated voltage clamps in the outputs
provide protection against inductive transients making the device suitable for power driver
applications such as relay, solenoids and other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +125 C
Low R
DSon
Eight Power EDNMOS transistor outputs of 100 mA continuous current
250 mA current limit capability
Output clamping voltage 33 V
30 mJ avalanche energy capability
All registers cleared with single input
Low power consumption
ESD protection:
HBM AEC-Q100-002 revision D exceeds 2500 V
CDM AEC-Q100-011 revision B exceeds 1000 V
3. Applications
LED sign
Graphic status panel
NPIC6C595-Q100
Power logic 8-bit shift register; open-drain outputs
Rev. 1 — 12 July 2012 Product data sheet