Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Shift register Shift register Open drain TSSOP 16

1. General description

The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a

storage register and open-drain outputs. Both the shift and storage register have separate

clocks. The device features a serial input (DS) and a serial output (Q7S) to enable

cascading and an asynchronous reset MR

input. A LOW on MR resets both the shift

input. The data in the shift register is transferred to the storage register on a

LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift

time in cascaded applications, the serial output QS7 is clocked out on the falling edge of

SHCP. Data in the storage register drives the gate of the output extended-drain NMOS

(EDNMOS) transistor whenever the output enable input (OE

) is LOW. A HIGH on OE

causes the outputs to assume a high-impedance OFF-state. Operation of the OE

input

does not affect the state of the registers. The open-drain outputs are 33 V/100 mA

continuous current extended-drain NMOS transistors designed for use in systems that

require moderate load power such as LEDs. Integrated voltage clamps in the outputs,

provide protection against inductive transients. These voltage clamps make the device

suitable for power driver applications such as relays, solenoids and other low-current or

medium-voltage loads.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply range 2.3 V to 5.5 V

 Low R

DSon

 Eight Power EDNMOS transistor outputs of 100 mA continuous current

 250 mA current limit capability

 Output clamping voltage 33 V

 30 mJ avalanche energy capability

 Enhanced cascading for multiple stages

 All registers cleared with single input

 Low power consumption

 ESD protection:

 HBM AEC-Q100-002 revision D exceeds 2500 V

 CDM AEC-Q100-011 revision B exceeds 1000 V

NPIC6C596A-Q100

Power logic 8-bit shift register; open-drain outputs

Rev. 1 — 18 October 2013 Product data sheet

Summary of content (20 pages)

PAGE 1
NPIC6C596A-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 1 — 18 October 2013 Product data sheet 1. General description The NPIC6C596A-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 3. Applications  LED sign  Graphic status panel  Fault status indicator 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 NPIC6C596APW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs VCC Qn 33 V GND GND aaa-002551 aaa-002550 Fig 3. Schematic of all inputs Fig 4. 67$*( '6 ' Schematic of open-drain outputs (Qn) 67$*( 72 4 ' 67$*( 4 ' 4 67$*( 6 &3 5 5 4 6 )) &3 &3 4 ' )) )) 5 6+&3 05 5 ' 5 ' 4 )) 4 )) &3 &3 67&3 2( *1' *1' DDD 4 Fig 5.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 7 6 5 4 3 2 1 0 5V SHCP GND 5V OE GND 5V DS GND 5V STCP GND 5V MR GND Q1 VOH VOL aaa-002553 Fig 6. Timing diagram 6. Pinning information 6.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 6.2 Pin description Table 2.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs Table 3. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 8. Recommended operating conditions Table 4. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage Conditions ID drain current pulsed drain output current; VCC = 5 V; Tamb = 25 C; all outputs on Tamb ambient temperature [1] Pulse duration  100 s and duty cycle  2 %. [2] Technique should limit Tj  Tamb to 10 C maximum. Min Typ Max Unit 2.3 - 5.5 V 0 - 5.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs Table 5. Static characteristics …continued At recommended operating conditions unless otherwise specified. Voltages are referenced to GND (ground = 0 V). Symbol Parameter RDSon drain-source on-state resistance Tamb = 25 C Conditions see Figure 17 and Figure 18 Min - 3.0 11  5.4 14  3.1 12  VCC = 3.0 V; ID = 50 mA VCC = 3.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 10.1 Test circuits and waveforms VI OE input VM GND tPHL tPLH 24 V Qn output LOW-to-OFF OFF-to-LOW VOL VY VY VX VX tf tr aaa-002557 Measurement points are given in Table 7. VOL is the typical output voltage drop that occurs with the output load. Fig 10.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs VI SHCP input VM GND tsu tsu th th VI DS input VM GND VOH VM Q7S output VOL aaa-002559 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 12. The data set-up and hold times for the serial data input (DS) Table 8.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs VI tW 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % VM positive pulse VM 10 % 0V tW 5V VDS = 15 V 1 7 15 WORD GENERATOR (1) 2 10 8 VCC MR RL SHCP Qn DS 3, 4, 5, 6 11, 12,13, 14 CL (2) STCP OE GND 16 aaa-002561 (1) The word generator has the following characteristics: tr, tf  10 ns; tW = 300 ns; pulsed repetition rate (PRR) = 5 kHz; ZO = 50 . (2) CL includes probe and jig capacitance.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs aaa-002562 1 aaa-002563 6 lCC (mA) IAL (A) 4 10-1 2 10-2 10-1 1 10 0 10-1 1 fi (MHz) Tamb = 25 C. Tamb = 40 C to 125 C; VCC = 5 V. Fig 15. Avalanche current (peak) versus time duration of avalanche DDD 5'6RQ ȍ 102 10 tAL (ms) Fig 16.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs aaa-002546 140 switching time (ns) 120 (1) (2) 100 (3) 80 60 (4) 40 20 0 -50 -25 0 25 50 75 100 125 Tamb (°C) Technique should limit TJ  TC to 10 C maximum. (1) tPLH. (2) tr. (3) tf. (4) tPHL. Fig 19. Switching time versus case temperature NPIC6C596A_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 18 October 2013 © NXP B.V. 2013.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test EDNMOS Extended Drain Negative Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13. Revision history Table 11.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only.
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NPIC6C596A-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .