Datasheet

NPIC6C596 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 2 — 4 July 2013 11 of 21
NXP Semiconductors
NPIC6C596
Power logic 8-bit shift register; open-drain outputs
(1) The open-drain Qn terminal under test is connected to test point K. All other terminals are connected together and connected to
test point A.
(2) The V
I
amplitude and R
G
are adjusted for dI/dt = 10 A/s. A V
I
double-pulse train is used to set I
F
= 0.1 A, where t
1
= 10 s, t
2
=
7 s and t
3
= 3 s.
Fig 13. Test circuit and waveform for measuring reverse recovery current
aaa-002560
I
F
DUT
Qn
15 V
driver
R
G
G
50 Ω
2500 μF
250 V
0.85 mH
K
(1)
A
(1)
t
1
t
2
t
3
V
I
(2)
0.1 A
di/dt = 10 A/μs
I
F
t
a
t
rr
0
25 % of l
RM
I
RM