Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Shift register Shift register Open drain TSSOP 16

1. General description

The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage

The device features a serial input (DS) and a serial output (Q7S) to enable cascading and

an asynchronous reset MR

input. A LOW on MR resets both the shift register and storage

the shift register is transferred to the storage register on a LOW-to-HIGH transition of the

STCP input. If both clocks are connected together, the shift register is always one clock

pulse ahead of the storage register. To provide additional hold time in cascaded

applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the

storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor

whenever the output enable input (OE

) is LOW. A HIGH on OE causes the outputs to

assume a high-impedance OFF-state. Operation of the OE

input does not affect the state

of the registers.

The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS

transistors designed for use in systems that require moderate load power such as LEDs.

Integrated voltage clamps in the outputs provide protection against inductive transients

making the device suitable for power driver applications such as relays, solenoids and

other low-current or medium-voltage loads.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +125 C

 Low R

DSon

 Eight Power EDNMOS transistor outputs of 100 mA continuous current

 250 mA current limit capability

 Output clamping voltage 33 V

 30 mJ avalanche energy capability

 Enhanced cascading for multiple stages

 All registers cleared with single input

 Low power consumption

 ESD protection:

 HBM AEC-Q100-002 revision D exceeds 2500 V

 CDM AEC-Q100-011 revision B exceeds 1000 V

NPIC6C596-Q100

Power logic 8-bit shift register; open-drain outputs

Rev. 2 — 4 July 2013 Product data sheet

Summary of content (21 pages)

PAGE 1
NPIC6C596-Q100 Power logic 8-bit shift register; open-drain outputs Rev. 2 — 4 July 2013 Product data sheet 1. General description The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR resets both the shift register and storage register.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 3. Applications  LED sign  Graphic status panel  Fault status indicator 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 NPIC6C596PW-Q100 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs VCC Qn 33 V GND GND aaa-002551 aaa-002550 Fig 3. Schematic of all inputs Fig 4. STAGE 0 DS D Schematic of open-drain outputs (Qn) STAGE 1 TO 6 Q D STAGE 7 Q D FF0 Q STAGE 7S CP Q7S FF7 CP R Q D FF7 CP R R SHCP MR R D Q R D FF Q FF CP CP STCP OE GND GND aaa-002552 Q0 Fig 5.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 7 6 5 4 3 2 1 0 SHCP 5V GND 5V OE GND 5V DS GND 5V STCP GND 5V MR GND Q1 VOH VOL aaa-002553 Fig 6. Timing diagram NPIC6C596_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 July 2013 © NXP B.V. 2013. All rights reserved.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 6. Pinning information 6.1 Pinning VCC 1 terminal 1 index area NPIC6C596-Q100 16 GND NPIC6C596-Q100 DS 2 15 SHCP VCC 1 16 GND Q0 3 14 Q7 DS 2 15 SHCP Q1 4 13 Q6 Q0 3 14 Q7 Q2 5 Q1 4 13 Q6 Q3 6 Q2 5 12 Q5 MR 7 Q3 6 11 Q4 MR 7 10 STCP OE 8 11 Q4 8 9 OE 10 STCP Q7S 9 12 Q5 GND(1) Q7S aaa-002555 Transparent top view aaa-002554 (1) This is not a supply pin.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage 0.5 +7.0 V VI input voltage VDS drain-source voltage power EDNMOS drain-source voltage 0.3 +7.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 7.1 Test circuit and waveform 5V 15 V VCC 7 15 WORD GENERATOR(1) 2 10 8 lD 1 MR SHCP DUT DS Qn 3-6, 11-14 tAL tw(2) 30 Ω 5V 1.5 mH 0V lAL = 200 mA ID VDS STCP OE V(BR)DSS = 33 V VDS GND min 16 aaa-002556 (1) The word generator has the following characteristics: tr, tf  10 ns; ZO = 50 . (2) The input pulse duration (tW) is increased until peak current IAL = 200 mA.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs Table 5. Static characteristics …continued At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL VCC = 5.0 V; Tamb = 25 C Conditions LOW-level output serial data output Q7S; VI = VIH or VIL voltage IO = 20 A; VCC = 4.5 V IO = 4 mA; VCC = 4.5 V Min Typ Unit Max - 0.005 0.1 V - 0.3 0.5 V IIH HIGH-level input current VCC = 5.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 10. Dynamic characteristics Table 6. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 14. Symbol Parameter VCC = 5.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 1/fmax VI SHCP input VM GND tW tPLH tPHL VOH VM Q7S output VOL aaa-002558 Measurement points are given in Table 7. VOL and VOH are the typical output voltage levels that occur with the output load. Fig 11. The shift clock (SHCP) to serial data output (Q7S) propagation delays with the minimum shift clock pulse width and maximum shift clock frequency Table 7.
PAGE 11
NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs K(1) Qn DUT 0.85 mH 2500 μF 250 V 0.1 A 15 V di/dt = 10 A/μs IF IF A(1) 0 t2 t1 25 % of lRM t3 driver RG VI(2) G IRM ta 50 Ω trr aaa-002560 (1) The open-drain Qn terminal under test is connected to test point K. All other terminals are connected together and connected to test point A. (2) The VI amplitude and RG are adjusted for dI/dt = 10 A/s. A VI double-pulse train is used to set IF = 0.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs VI tW 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % VM positive pulse VM 10 % 0V tW 5V VDS = 15 V 1 7 15 WORD GENERATOR (1) 2 10 8 VCC MR RL SHCP Qn DS 3, 4, 5, 6 11, 12,13, 14 CL (2) STCP OE GND 16 aaa-002561 (1) The word generator has the following characteristics: tr, tf  10 ns; tW = 300 ns; pulsed repetition rate (PRR) = 5 kHz; ZO = 50 . (2) CL includes probe and jig capacitance.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs aaa-002562 1 aaa-002563 6 lCC (mA) IAL (A) 4 10-1 2 10-2 10-1 1 0 10-1 10 1 fi (MHz) Tamb = 25 C. Tamb = 40 C to 125 C; VCC = 5 V. Fig 15. Avalanche current (peak) versus time duration of avalanche aaa-002564 5 4 Fig 16.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs aaa-002546 140 switching time (ns) 120 (1) (2) 100 (3) 80 60 (4) 40 20 0 -50 -25 0 25 50 75 100 125 Tamb (°C) Technique should limit TJ  TC to 10 C maximum. (1) tPLH. (2) tr. (3) tf. (4) tPHL. Fig 19. Switching time versus case temperature NPIC6C596_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 4 July 2013 © NXP B.V. 2013.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 11. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 7 y y1 C v M C A B w M C b L 1 8 Eh e 16 9 15 10 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test EDNMOS Extended Drain Negative Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model TTL Transistor-Transistor Logic 13. Revision history Table 11.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only.
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NPIC6C596-Q100 NXP Semiconductors Power logic 8-bit shift register; open-drain outputs 16. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 10.1 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .