Datasheet
NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 3 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
4. Functional diagram
5. Pinning information
5.1 Pinning
5.1.1 8-bit in TSSOP20 and DHVQFN20 packages
Fig 1. Logic diagram of NVT2008/10 (positive logic)
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A1
An
VREFA
GND
VREFB
B1
Bn
EN
SW
SW
NVT20xx
Fig 2. Pin configuration for TSSOP20 Fig 3. Pin configuration for DHVQFN20
NVT2008PW
GND EN
VREFA VREFB
A1 B1
A2 B2
A3 B3
A4 B4
A5 B5
A6 B6
A7 B7
A8 B8
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1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
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NVT2008BQ
Transparent top view
B7
A6
A7
B6
A5 B5
A4 B4
A3 B3
A2 B2
A1 B1
VREFA VREFB
A8
B8
GND
EN
9
12
8 13
7 14
6 15
5 16
4 17
3 18
2 19
10
11
1
20
terminal 1
index area