Datasheet

NVT2008_NVT2010 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 3 — 27 January 2014 8 of 33
NXP Semiconductors
NVT2008; NVT2010
Bidirectional voltage-level translator
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins pulled
to HIGH side V
pu(D)
through a pull-up resistor (typically 200 k). This allows VREFB to
regulate the EN input. A filter capacitor on VREFB is recommended. The master output
driver can be totem pole or open-drain (pull-up resistors may be required) and the slave
device output can be totem pole or open-drain (pull-up resistors are required to pull the Bn
outputs to V
pu(D)
). However, if either output is totem-pole, data must be unidirectional or
the outputs must be 3-stateable and be controlled by some direction-control mechanism
to prevent HIGH-to-LOW contentions in either direction. If both outputs are open-drain, no
direction control is needed.
The reference supply voltage (V
ref(A)
) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 k resistor to a 3.3 V to 5.5 V V
pu(D)
power supply, and V
ref(A)
is set between 1.0 V and (V
pu(D)
 1 V), the output of each An
has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to V
pu(D)
.
Fig 9. Bidirectional translation to multiple higher voltage levels
EN
VREFB
002aae133
B1
B2
200 kΩ
CHIPSET I/O
V
CC
5 V
totem pole or
open-drain I/O
GND
VREFA
A1
A2
B3
V
CC
Bn
3.3 V
A3
An
CPU I/O
V
CORE
1.8 V
1.5 V
1.2 V
1.0 V
SW
NVT20XX
SW
SW
CHIPSET I/O
SW
B4A4
B5A5
SW
SW
B6A6
SW