NX5P2924B Logic controlled high-side power switch Rev. 1 — 24 February 2014 Product data sheet 1. General description The NX5P2924B is a high-side load switch which features a low ON resistance N-channel MOSFET with controlled slew rate that supports 2.5 A of continuous current. Designed for operation from 0.8 V to 5.5 V, it is used in power domain isolation applications to reduce power dissipation and extend battery life.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 4. Ordering information Table 1. Ordering information Type number NX5P2924BUK Package Temperature range Name Description Version 40 C to +85 C WLCSP6 wafer level chip-scale package; 6 bumps; 0.87 x 1.37 x 0.5 mm NX5P2924B 5. Marking Table 2. Marking codes Type number Marking code NX5P2924BUK 4B 6. Functional diagram EN VIN VOUT 001aao342 Fig 1.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 7. Pinning information 7.1 Pinning EXPS $ 1; 3 % LQGH[ DUHD $ $ 9287 9,1 % % 9287 9,1 & & *1' (1 7UDQVSDUHQW WRS YLHZ 7UDQVSDUHQW WRS YLHZ DDD Fig 3. Pin configuration for WLCSP6 DDD Fig 4. Ball mapping for WLCSP6 7.2 Pin description Table 3.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter input voltage VI Conditions Min Max Unit input EN [1] 0.5 +6.0 V 0.5 +6.0 V 0.5 VI(VIN) V input VIN [2] VSW switch voltage output VOUT [2] IIK input clamping current input EN: VI(EN) < 0.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 11. Thermal characteristics Table 7. Symbol Rth(j-a) [1] Thermal characteristics Parameter Conditions [1] thermal resistance from junction to ambient Typ Unit 139 K/W Rth(j-a) is dependent upon board layout. To minimize Rth(j-a), ensure that all pins have a solid connection to larger copper layer areas. In multi-layer PCBs, the second layer should be used to create a large heat spreader area below the device.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch Table 8. Static characteristics …continued VI(VIN) = 1.0 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V). …continued Symbol Parameter I(VIN) IS(OFF) supply current OFF-state leakage current Tamb = 25 C Conditions Tamb = 40 C to +85 C Unit Min Typ[1] Max Min Max EN = HIGH; VI(VIN) = 1.0 V; see Figure 5 and Figure 6 - 25 - - 35 A EN = HIGH; VI(VIN) = 1.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 12.1 Graphs DDD , 9,1 $ DDD , 9,1 $ 7DPE & 9, 9,1 9 VI(EN) = VI(VIN). VI(EN) = VI(VIN). (1) VI(VIN) = 5.5 V. (1) Tamb = 85 C. (2) VI(VIN) = 3.6 V. (2) Tamb = 25 C. (3) VI(VIN) = 1.8 V. (3) Tamb = 40 C. (4) VI(VIN) = 1.0 V. Fig 5.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch DDD DDD , 9,1 Q$ , 9,1 Q$ 7DPE & (1) VI(VIN) = 1.8 V. (1) Tamb = 85 C. (2) VI(VIN) = 3.6 V. (2) Tamb = 25 C. (3) VI(VIN) = 5.5 V. (3) Tamb = 40 C. Fig 9. Typical OFF-state leakage current versus temperature 9, 9,1 9 Fig 10.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch DDD 521 Pȍ DDD 521 Pȍ 7DPE & (1) VI(VIN) = 1.0 V. (1) Tamb = 85 C. (2) VI(VIN) = 3.6 V. (2) Tamb = 25 C. Product data sheet 9, 9,1 9 (3) Tamb = 40 C. (3) VI(VIN) = 5.5 V. Fig 12. ON resistance versus temperature NX5P2924B Fig 13.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 13. Dynamic characteristics Table 10. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for test circuit, see Figure 15.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 13.1 Waveforms, graphs and test circuit 9, (1 LQSXW 90 *1' WRQ WRII WGLV WHQ 92+ 9< 9< 9287 RXWSXW 9; *1' 9; W7/+ W7+/ DDD Measurement points are given in Table 11. Logic level: VOH is the typical output voltage that occurs with the output load. Fig 14. Switching times Table 11. Measurement points Supply voltage EN Input Output VI(VIN) VM VX VY 1.0 V to 5.5 V 0.5 VI(EN) 0.1 VOH 0.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch DDD 9287 (1 9 ,, 9,1 P$ DDD 9287 (1 9 ,, 9,1 P$ W XV W XV VI(VIN) = 1 V; RL = 10 ; CL = 0.1 F; Tamb = 25 C. VI(VIN) = 3.6 V; RL = 10 ; CL = 0.1 F; Tamb = 25 C. (1) VOUT (1) VOUT (2) EN (2) EN (3) II(VIN) (3) II(VIN) Fig 16.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch DDD 9287 (1 9 ,, 9,1 P$ DDD 9287 (1 9 W XV W XV VI(VIN) = 3.6 V; RL = 10 ; CL = 20 F; Tamb = 25 C. VI(VIN) = 3.6 V; RL = 10 ; CL = 20 F; Tamb = 25 C (1) VOUT (1) VOUT (2) EN (2) EN (3) II(VIN) Fig 20. Typical enable time at VI(VIN) = 3.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 14.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 15. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model IEC International Electrotechnical Commission MOSFET Metal-Oxide Semiconductor Field Effect Transistor 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes NX5P2924B v.
NX5P2924B NXP Semiconductors Logic controlled high-side power switch 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NX5P2924B NXP Semiconductors Logic controlled high-side power switch 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 12.1 12.2 12.3 13 13.1 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . .