PBSS4032SPN 30 V NPN/PNP low VCEsat (BISS) transistor Rev. 2 — 14 October 2010 Product data sheet 1. Product profile 1.1 General description NPN/PNP low VCEsat Breakthrough In Small Signal (BISS) transistor in a SOT96-1 (SO8) medium power Surface-Mounted Device (SMD) plastic package. Table 1. Product overview Type number PBSS4032SPN Package NXP Name NPN/NPN complement SOT96-1 SO8 PBSS4032SN PNP/PNP complement PBSS4032SP 1.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor Table 2. Quick reference data …continued Symbol Parameter Conditions Min Typ Max Unit open base - - −30 V - - −4.8 A - - −10 A - 65 98 mΩ TR2; PNP low VCEsat transistor VCEO collector-emitter voltage IC collector current ICM peak collector current single pulse; tp ≤ 1 ms RCEsat collector-emitter saturation resistance IC = −4 A; IB = −0.4 A [1] [1] Pulse test: tp ≤ 300 μs; δ ≤ 0.02. 2.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 5. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit collector current - 5.7 A collector current - −4.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac302 3.0 Ptot (W) (1) 2.0 (2) 1.0 0.0 −75 (3) −25 25 75 125 175 Tamb (°C) (1) Ceramic PCB, Al2O3, standard footprint (2) FR4 PCB, mounting pad for collector 1 cm2 (3) FR4 PCB, standard footprint Fig 1. Per device: Power derating curves 6. Thermal characteristics Table 7.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac303 103 Zth(j-a) (K/W) duty cycle = 1 0.75 102 0.5 0.33 0.2 0.1 10 0.05 0.02 0.01 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 103 tp (s) FR4 PCB, standard footprint Fig 2. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 006aac304 103 Zth(j-a) (K/W) duty cycle = 1 102 0.75 0.5 0.33 0.2 0.1 10 0.05 0.02 0.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac305 102 duty cycle = 1 0.75 Zth(j-a) (K/W) 0.5 0.33 0.2 10 0.1 0.05 0.02 0.01 1 0 10−1 10−5 10−4 10−3 10−2 10−1 1 10 102 103 tp (s) Ceramic PCB, Al2O3, standard footprint Fig 4. Per transistor: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values PBSS4032SPN Product data sheet All information provided in this document is subject to legal disclaimers. Rev.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 7. Characteristics Table 8. Characteristics Tamb = 25 °C unless otherwise specified.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor Table 8. Characteristics …continued Tamb = 25 °C unless otherwise specified.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac306 1000 006aac307 12.0 hFE IB (mA) = 70 IC (A) (1) 800 56 42 8.0 (2) 600 63 49 35 28 21 14 400 (3) 4.0 7 200 0 10−1 1 102 10 0.0 0.0 103 104 IC (mA) 1.0 2.0 3.0 4.0 5.0 VCE (V) Tamb = 25 °C VCE = 2 V (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 5. TR1 (NPN): DC current gain as a function of collector current; typical values Fig 6. 006aac308 1.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac310 1 006aac311 1 VCEsat (V) VCEsat (V) 10−1 10−1 (1) (1) (2) (2) (3) 10−2 10−1 1 10 (3) 102 103 104 IC (mA) 10−2 10−1 1 102 103 104 IC (mA) Tamb = 25 °C IC/IB = 20 (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB = 10 Fig 9. 10 TR1 (NPN): Collector-emitter saturation voltage as a function of collector current; typical values 006aac312 103 Fig 10.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac314 800 hFE 006aac315 −12.0 IB (mA) = −600 IC (A) (1) −480 −360 600 −8.0 −240 (2) −540 −420 −300 −180 −120 400 −60 −4.0 (3) 200 0 −10−1 −1 −10 −102 −103 −104 IC (mA) 0.0 0.0 VCE = −2 V −1.0 −2.0 −3.0 −4.0 −5.0 VCE (V) Tamb = 25 °C (1) Tamb = 100 °C (2) Tamb = 25 °C (3) Tamb = −55 °C Fig 13. TR2 (PNP): DC current gain as a function of collector current; typical values 006aac316 −1.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 006aac318 −1 006aac319 −1 VCEsat (V) VCEsat (V) −10−1 −10−1 (1) (1) (2) (2) (3) −10−2 −10−1 −1 (3) −10 −102 −103 −104 IC (mA) −10−2 −10−1 −1 −10 −102 −103 −104 IC (mA) Tamb = 25 °C IC/IB = 20 (1) Tamb = 100 °C (1) IC/IB = 100 (2) Tamb = 25 °C (2) IC/IB = 50 (3) Tamb = −55 °C (3) IC/IB = 10 Fig 17.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 8. Test information IB input pulse (idealized waveform) 90 % IBon (100 %) 10 % IBoff output pulse (idealized waveform) IC 90 % IC (100 %) 10 % t td ts tr ton tf toff 006aaa003 Fig 21. TR1 (NPN): BISS transistor switching time definition VBB RB VCC RC Vo (probe) oscilloscope 450 Ω (probe) 450 Ω oscilloscope R2 VI DUT R1 mlb826 VCC = 12.5 V; IC = 1 A; IBon = 0.05 A; IBoff = −0.05 A Fig 22.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor − IB input pulse (idealized waveform) 90 % − I Bon (100 %) 10 % − I Boff output pulse (idealized waveform) − IC 90 % − I C (100 %) 10 % t td ts tr t on tf t off 006aaa266 Fig 23. TR2 (PNP): BISS transistor switching time definition VBB RB VCC RC Vo (probe) oscilloscope 450 Ω (probe) 450 Ω oscilloscope R2 VI DUT R1 mgd624 VCC = −12.5 V; IC = −1 A; IBon = −0.05 A; IBoff = 0.05 A Fig 24.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 9. Package outline 5.0 4.8 1.75 1.0 0.4 6.2 5.8 4.0 3.8 pin 1 index 1.27 0.49 0.36 Dimensions in mm 0.25 0.19 03-02-18 Fig 25. Package outline SOT96-1 (SO8) 10. Packing information Table 9. Packing methods The indicated -xxx are the last three digits of the 12NC ordering code.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 11. Soldering 5.50 0.60 (8×) 1.30 4.00 6.60 7.00 1.27 (6×) solder lands occupied area placement accuracy ± 0.25 Dimensions in mm sot096-1_fr Fig 26. Reflow soldering footprint SOT96-1 (SO8) 1.20 (2×) 0.60 (6×) enlarged solder land 0.3 (2×) 1.30 4.00 6.60 7.00 1.27 (6×) 5.50 board direction solder lands occupied area solder resist placement accurracy ± 0.25 Dimensions in mm sot096-1_fw Fig 27.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 12. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes PBSS4032SPN v.2 20101014 Product data sheet - PBSS4032SPN v.1 Modifications: PBSS4032SPN v.1 PBSS4032SPN Product data sheet • Figure 1 “Per device: Power derating curves”: updated. 20100714 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 13. Legal information 13.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 13.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 14. Contact information For more information, please visit: http://www.nxp.
PBSS4032SPN NXP Semiconductors 30 V NPN/PNP low VCEsat (BISS) transistor 15. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 10 11 12 13 13.1 13.2 13.3 13.4 14 15 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . .