Datasheet

PCA9306 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 8 — 22 January 2014 5 of 35
NXP Semiconductors
PCA9306
Dual bidirectional I
2
C-bus and SMBus voltage-level translator
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration for TSSOP8
(DP1)
Fig 3. Pin configuration for TSSOP8 (DP)
(MSOP8)
Fig 4. Pin configuration for VSSOP8 (DC) Fig 5. Pin configuration for VSSOP8
(DC1; DC1/DG)
Fig 6. Pin configuration for SO8 Fig 7. Pin configuration for XQFN8
PCA9306DP1
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aab842
1
2
3
4
6
5
8
7
PCA9306DP
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aac373
1
2
3
4
6
5
8
7
PCA9306DC
VREF1 EN
SCL1 VREF2
SDA1 SCL2
GND SDA2
002aac374
1
2
3
4
6
5
8
7
PCA9306DC1
PCA9306DC1/DG
GND EN
VREF1 VREF2
SCL1 SCL2
SDA1 SDA2
002aab843
1
2
3
4
6
5
8
7
PCA9306D
GND EN
VREF1 VREF2
SCL1
SCL2
SDA1 SDA2
002aac372
1
2
3
4
6
5
8
7
002aac375
SCL2VREF1
VREF2
EN
SDA2
GND
SDA1
SCL1
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
PCA9306GM