PCA9629A Fm+ I2C-bus advanced stepper motor controller Rev. 2 — 21 March 2014 Product data sheet 1. General description The PCA9629A is an I2C-bus controlled low-power CMOS device that provides all the logic and control required to drive a four phase stepper motor. PCA9629A is intended to be used with external high current drivers to drive the motor coils. The PCA9629A supports three stepper motor drive formats: one-phase (wave drive), two-phase, and half-step.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Programmable steps with clockwise and/or counter-clockwise control Direction control of motor shaft Selectable active hold (last state), power on, power off or released states for motor shaft 32-bit step counter to count output steps Interrupt features Active LOW open-drain interrupt output Programmable watchdog timer with option to generate interrupt, reset device or stop motor Programmable motor stop interrupt S
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Variable-speed fans and pumps Vending machines 4. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9629APW PA9629A TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 4.1 Ordering options Table 2.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 6. Pinning information 6.1 Pinning P0/DET 1 16 VDD P1 2 15 SDA P2 3 14 SCL P3 4 AD0 5 AD1 6 11 OUT1 RESET 7 10 OUT2 VSS 8 PCA9629APW 13 INT 12 OUT0 9 OUT3 002aah528 Fig 2. Pin configuration for TSSOP16 6.2 Pin description Table 3.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7. Functional description Refer to Figure 1 “PCA9629A block diagram”. 7.1 Device address Following a START condition, the bus master must send the target slave address followed by a read or write operation. The slave address of the PCA9629A is shown in Figure 3. Slave address pins AD1 and AD0 choose one of 16 slave addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and AD0.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.2 Command register Following the successful acknowledgement of the slave address and a write bit, the bus master sends a byte to the PCA9629A. This byte is stored in the Command register. AI - D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 default at power-up or after RESET register number Auto-Increment Fig 4.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 5.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.1 MODE — Mode register Table 6. MODE - Mode register (address 00h) bit description Legend: * default value. Address Register Bit Access Value Description 00h MODE 7 - 0* not used 6 R/W 1 Low-power sleep mode. Oscillator off. 0* Normal mode.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.1.2 Disable interrupt output pin (bit 5) This feature is useful when the host/micro/master does not want the INT pin to toggle when interrupts occur. Within PCA9629A, when interrupts are enabled and interrupt event occurs, the actions related to the interrupt event are still carried out. However, if bit 5 = 1, the INT pin does not show the activation of interrupt because the pin is disabled.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.2.1 WDTOI — WatchDog Time-Out Interval register The watchdog time-out interval should be programmed in this register. The default value is FFh, which indicates a 255 second time-out interval. The smallest value for the time-out interval is 01h, which indicates a one-second time-out interval. Watchdog operation cannot be enabled with a zero second time-out interval.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.3 IO_CFG — I/O Configuration register The lower four bits of this register configures the direction of the I/O pins P0 to P3. If a bit in [3:0] is set (written with logic 1), the corresponding port pin is enabled as an input with high-impedance output driver.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 10. INTMODE - Interrupt mode register (address 04h) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.5 MSK — Mask interrupt register Upon power-up, all the internal interrupt latches are reset and interrupt flags cleared and interrupt mask bits [4:0] are set to logic 1, thus disabling interrupts from input ports P0 to P3 and motor stop caused by bit 7 in MCNTL register. Interrupts may be enabled by setting corresponding mask bits to logic 0. Table 11.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller [2] This bit will be cleared by any reset events except the watchdog reset event. Upon power-up or any reset events, INTSTAT register bits [4:0] are cleared (= 0), thus clearing the interrupt flags. Change in logic level at GPIO pins P0 to P3 configured as inputs or motor stopped will cause generation of interrupt when not masked using MSK register.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.8.1 INT_MTR_ACT — Interrupt motor action control register Table 14. INT_MTR_ACT - Interrupt motor action control register (address 08h) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller When an interrupt occurs, if the motor is programmed in bit [7:5] to re-start motor on that interrupt, the following sequence of events takes place: 1. The current motor speed and operation is changing and re-start new motor speed and operation based on these new motor parameter registers setting.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 3.3 V 5V 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ VDD MASTER CONTROLLER INT RST generates INTP0 P0 SCL P1 SDA P2 INT P3 generates INTP1 sensor 1 sensor 0 RESET PCA9629A position B OUT3 OUT2 OUT1 OUT0 AD1 AD0 12 V EXTERNAL HIGH CURRENT DRIVER position A electrical stepper motor M VSS 002aah546 Fig 7.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.9 EXTRASTEPS0, EXTRASTEPS1 — Extra steps count for INTP0, INTP1 control register Table 15. EXTRASTEPS0, EXTRASTEPS1 - Extra steps count for INTP0, INTP1 register (address 09h, 0Ah) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 16. OP_CFG_PHS - Output Port Configuration and Phase control register (address 0Bh) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 17. OP_STAT_TO - Output state and time-out control register (address 0Ch) bit description Legend: * default value. Address Register Bit Access 0Ch OP_STAT_TO 7:5 R/W Description Motor stop time-out timer. The output state will drive all logic 0 when motor is stopped and this timer counts down to zero.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 19.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.13 RDCNTL — Ramp-down control register Table 20. RDCNTL - Ramp-down control register (address 0Eh) bit description Legend: * default value.
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PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller speed keep rotating 1536 steps in final speed (re-enable ramp-up or ramp-down has no effect during the final speed) decrease step pulse width by 24 μs (second ramp speed) decrease step pulse width by 48 μs (first ramp speed) (re-enable ramp-up bit) increase step pulse width by 48 μs (third ramp speed) (re-enable ramp-down bit) increase step pulse width by 24 μs(fourth ramp speed) ramp start speed (49.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller In the duration between end of ramp-up and beginning of ramp-down, the interrupt based controls (if enabled) can affect the operation of the motor. In this region, Section 7.3.8 gives the priority of events when both interrupt-based control and ramp control are enabled together. 7.3.14 PMA — Perform multiple of actions control register Table 21.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.16 LOOPDLY_CCW — Loop delay timer for CCW to CW control register This feature is used to make the motor wait for a certain amount of time before reversing its direction from counter-clockwise to clockwise rotation. There are two situations in which the motor must reverse its direction of rotation: • The user requests both clockwise and counter-clockwise rotation (also known as auto reversal mode).
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.19 CWPWL, CWPWH — Clockwise step pulse width register This register determines the step pulse width used for the phase sequence output waveforms during ClockWise (CW) rotation. Table 26. CWPWL, CWPWH - Clockwise step pulse width control register (address 16h, 17h) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.20 CCWPWL, CCWPWH — Counter-clockwise step pulse width register This register determines the step pulse width used for the phase sequence output waveforms during Counter-ClockWise (CCW) rotation. Table 28. CCWPWL, CCWPWH - Counter-clockwise step pulse width control register (address 18h, 19h) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.3.21 MCNTL — Motor control register This register acts like the master control panel for driving the motor. It determines the type of motor operation and controls the starting/stopping or re-start new speed of the motor. The registers from address 08h (INT_MTR_ACT) to 19h (CCWPWH) are referred to as the motor parameter registers.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller When the current operation is completed, the motor stops and this bit is cleared. The completion of motor operation can be checked by reading this bit or detecting motor stop interrupt if motor stop interrupt is enabled in MSK register (bit 4 = 0). After the motor has stopped, the motor parameter registers can be updated and the motor can be started again.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller • Re-start motor request issued when the motor is already in the stopped state is ignored. • Re-start motor request when the current motor is stopped and waiting for the loop delay time in auto-reversal mode is ignored.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller speed 12.29 ms if S0 < S1, ramp up to speed S1 motor running at S1 speed (12.294 ms) (re-start motor will wait for the ramp up to complete) second operation (128 steps) 24.58 ms third operation (total of steps) if S0 > S1, ramp down to speed S1 36.87 ms motor running at S1 speed (36.87 ms) first operation 49.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 2. If P0 input state is LOW, then motor is started until the P0 input state is detected as HIGH (motor is back to right position). User can periodically send this command to keep motor in home-position without polling the P0 input state. 7.3.21.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller LSB in SUBADRx register is a read-only bit (0). When subaddress control bits [3:1] in MODE register is set to logic 1, the corresponding I2C-bus subaddress can be used during either an I2C-bus read or write sequence. 7.3.23 ALLCALLADR — All Call I2C-bus address Table 32. ALLCALLADR - All Call I2C-bus address register (address 1Eh) bit description Legend: * default value.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.4 Motor coil excitation Initially, after a power-up of the device, when the motor is started for the first time, the first coil that is energized is OUT0 (if the motor is turning in the clockwise direction), or OUT3 (if the motor is turning in the counter-clockwise direction). This very first step (after a power-up) is not counted towards the number steps the motor is required to move (it is the reference step).
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.7 Software reset The Software Reset Call allows all the devices in the I2C-bus to be reset to the power-up state value through a specific formatted I2C-bus command. To be performed correctly, it implies that the I2C-bus is functional and that there is no device hanging the bus. The maximum wait time after software reset is 1 ms (typical). The SWRST Call function is defined as the following: 1.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.9.2 Two-phase drive In two-phase drive method, two windings are energized at any given time. In case of two-phase drive, the torque output of the unipolar wound motor is lower than the bipolar motor (for motors with the same winding parameters) since the unipolar motor uses only 50 % of the available winding, while the bipolar motor uses the entire winding.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 7.9.3 Half-step drive (one-phase and two-phase on) ‘Half-step drive’ combines both wave and two-phase (one-phase and two-phase on) drive modes. This results in angular movements that are half of those in 1- or 2-phases-on drive modes. Half-stepping can reduce a phenomenon referred to as resonance, which can be experienced in 1- or 2-phases-on drive modes.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 8. Characteristics of the I2C-bus The I2C-bus is for two-way, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 21. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 10. Application design-in information 3.3 V 5V 1.6 kΩ 1.6 kΩ 1.1 kΩ 2 kΩ VDD MASTER CONTROLLER INT RST generates INTP0 P0 SCL P1 SDA P2 INT P3 generates INTP1 sensor 1 sensor 0 RESET PCA9629A position B OUT3 OUT2 OUT1 OUT0 AD1 AD0 12 V EXTERNAL HIGH CURRENT DRIVER position A electrical stepper motor M VSS 002aah546 Device address configured as 0100 0000b for this example. Fig 23. Typical application 10.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 10.2 Considerations when using GPIO pins P0 to P3 as inputs For proper operation of GPIO pins as inputs, the signals at the inputs must be free from any glitches or noise. The signals must be logic level inputs. For example, outputs from sensors must provide logic level signals at the input pins of PCA9629A. This may require signal conditioning at the outputs of sensors.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller • If interrupt P0 happens, then it reverses rotation right away and start rotating in the CCW direction for the specified number of steps. • Before the specified number of steps is completed in the CCW direction, if interrupt P1 happens, then it again reverses its rotation right away and start rotating in the CW direction for the specified number of steps.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Table 38. Static characteristics …continued VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit OUT0 to OUT3 outputs LOW-level output current IOL IOL(tot) VOH VOL = 0.4 V; VDD = 4.5 V [2] 20 22 - mA VOL = 0.5 V; VDD = 4.5 V [2] 25 28 - mA total LOW-level output current VOL = 0.5 V; VDD = 4.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller VDD = 5.0 V VDD = 5.0 V PMOS data[0:3] I/O CONTROL PMOS data[0:3] OUTPUT CONTROL OUT[0:3] (output) enable P[0:3] (I/O) NMOS NMOS input data [0:3] 002aag588 002aag587 Fig 24. OUT[0:3] output equivalent circuit PCA9629A Product data sheet Fig 25. P[0:3] input/output equivalent circuit All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 March 2014 © NXP Semiconductors N.V. 2014.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 13. Dynamic characteristics Table 39. Dynamic characteristics VDD = 4.5 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Oscillator frequency = 1 MHz 3 % at 40 C to +85 C (see Figure 28).
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 26. Definition of timing ACK or read cycle START SCL SDA 30 % RESET 50 % 50 % 50 % trec(rst) tw(rst) 50 % P0 to P3 output off 002aag778 Fig 27. Reset timing aaa-010095 1.02 fosc (MHz) 1.01 1.00 0.99 0.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 14. Test information VDD PULSE GENERATOR VI RL 500 Ω VO 2VDD open VSS DUT CL 50 pF RT 500 Ω 002aac019 RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generators. Fig 29.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 32. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 18. Soldering: PCB footprints Footprint information for reflow soldering of TSSOP16 package SOT403-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 5.600 5.300 5.800 7.450 sot403-1_fr Fig 33.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 19. Abbreviations Table 42.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 23. Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.3 7.3.2 7.3.2.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Ordering options . . . . . . . . . . . . . . . . . . . . . . . .
PCA9629A NXP Semiconductors Fm+ I2C-bus advanced stepper motor controller 17 17.1 17.2 17.3 17.4 18 19 20 21 21.1 21.2 21.3 21.4 22 23 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering . . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . Soldering: PCB footprints. . . . . . . . . . . . . . . . Abbreviations . . .