Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsPCA9661B,118

1. General description

The PCA9661 is an advanced single master mode I

C-bus controller. It is a fourth

generation bus controller designed for data intensive I

C-bus data transfers. It has one

C-bus channel with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+)

open-drain topology. The serial channel has a generous 4352 byte data buffer which

makes the PCA9661 the ideal companion to any CPU that needs to transmit and receive

large amounts of serial data with minimal interruptions.

The PCA9661 is a 8-bit parallel-bus to I

C-bus protocol converter. It can be configured to

communicate with up to 64 slaves in one serial sequence with no intervention from the

CPU. The controller also has a sequence loop control feature that allows it to

automatically retransmit a stored sequence.

Its onboard oscillator and PLL allow the controller to generate the clocks for the I

C-bus

and for the interval timer used in sequence looping. This feature greatly reduces CPU

overhead when data refresh is required in fault tolerant applications.

An external trigger input allows data synchronization with external events. The trigger

signal controls the rate at which a stored sequence is re-transmitted over the I

C-bus.

Error reporting is handled at the transaction level, channel level, and controller level.

A simple interrupt tree and interrupt masks allow further customization of interrupt

management.

The controller parallel bus interface runs at 3.3 V and the I

C-bus I/Os logic levels are

referenced to a dedicated V

DD(IO)

input pin with a range of 3.0 V to 5.5 V.

2. Features and benefits

 Parallel-bus to I

C-bus protocol converter and interface

 1 Mbit/s and up to 30 mA SCL/SDA I

Fast-mode Plus (Fm+) capability

 Internal oscillator trimmed to 1 % accuracy reduces external components

 4352-byte buffer for the Fm+ channel

 Three levels of reset: individual software channel reset, global software reset, global

hardware RESET

 Communicates with up to 64 slaves in one serial sequence

 Sequence looping with interval timer

 Supports SCL clock stretching

 JTAG port available for boundary scan testing during board manufacturing process

 Trigger input synchronizes serial communication exactly with external events

 Maskable interrupts

PCA9661

Parallel bus to 1 channel Fm+ I

C-bus controller

Rev. 1 — 4 August 2011 Product data sheet

Summary of content (63 pages)

PAGE 1
PCA9661 Parallel bus to 1 channel Fm+ I2C-bus controller Rev. 1 — 4 August 2011 Product data sheet 1. General description The PCA9661 is an advanced single master mode I2C-bus controller. It is a fourth generation bus controller designed for data intensive I2C-bus data transfers. It has one I2C-bus channel with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller      Fast-mode Plus I2C-bus capable and compatible with SMBus Operating supply voltage: 3.0 V to 3.6 V (device and host interface) I2C-bus I/O supply voltage: 3.0 V to 5.5 V Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ESD protection exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Packages offered: LQFP48 3.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 5.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 6. Pinning information 37 D0 38 D1 39 VSS 40 VDD 41 D2 42 D3 43 VSS 44 VDD 45 D4 46 D5 D6 1 36 RESET D7 2 35 VSS A0 3 34 TRIG A1 4 33 CE A2 5 32 RD A3 6 VDD 7 VSS 8 29 VSS A4 9 28 SCL0 A5 10 27 SDA0 A6 11 26 n.c. A7 12 25 n.c. 31 WR VDD(IO) 24 VSS(IO) 23 n.c. 22 30 VDD n.c. 21 INT 20 VSS(PLL) 19 VDD(PLL) 18 TDO 17 TDI 16 TCK 15 TMS 14 PCA9661B TRST 13 Fig 2.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 2. Pin description …continued Symbol Pin Type Description TRST 13 I JTAG test reset input. For normal operation, hold LOW (VSS). TMS 14 I JTAG test mode select input. For normal operation, hold HIGH (VDD). TCK 15 I JTAG test clock input. For normal operation, hold HIGH (VDD). TDI 16 I JTAG test data in input. For normal operation, hold HIGH (VDD). TDO 17 O JTAG test data out output.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7. Functional description 7.1 General The PCA9661 acts as an interface device between standard high-speed parallel buses and the serial I2C-bus. On the I2C-bus, it acts as a master. Data transfer between the I2C-bus and the parallel-bus host is carried out on a buffered basis, using either an interrupt or polled handshake. 7.2 Internal oscillator and PLL The PCA9661 contains an internal 12.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller After sending all the commands and data it wanted to the I2C-bus controller, the host writes to the CONTROL register to begin data transmission on the serial channel. The transactions will be sent on the I2C-bus in the order in which the slave addresses are listed in the SLATABLE, separated by a RESTART condition. The last transaction in the sequence will end with a STOP condition.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.4 Error reporting and handling In case of any transaction error conditions, the device will load the transaction error status in the STATUS0_[n], generate an interrupt, if unmasked, by pulling down the INT pin and update the CHSTATUS and CTRLSTATUS registers. The status for the individual SLA addresses will be stored in the STATUS0_[n] registers. In the event of a NACK from a slave, there are two possible courses of action.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.1 Channel registers 7.5.1.1 STATUS0_[n] — Transaction status registers STATUS0_[n] is an 8-bit  64 read-only register that provides status information for a given transaction. Only the 5 lower bits are used; the top bits will always read 0. When bits [4:2] are set, a channel interrupt is requested (the INT pin is asserted LOW). A read to STATUS0_[n] register will clear its status.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller After STA is set: STATUS0_[0] = 2 STATUS0_[1] = 1 STATUS0_[2] = 1 STATUS0_[3] = 0 : Since there is no timing requirement in setting the STA bit after the initialization, the device will update the first status when the STA bit is set and will always go from 0 to 2 (Idle to Transaction active). 7.5.1.2 CONTROL — Control register CONTROL is an 8-bit register.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 5. CONTROL - Control register bit description …continued Address: Channel 0 = C0h. Legend: * reset value Bit Symbol Access 4 TP R/W 3 TE Value Description Trigger polarity bit. Cannot be changed while channel is active. 1 Trigger will be detected on a falling edge. 0* Trigger will be detected on a rising edge. R/W Trigger Enable (TE) bit controls the trigger input used for frame refresh.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior Channel state (initialization steps) Next write action by host Idle (reset, TRANCONFIG, SLATABLE, DATA, STA = 0) 1 0 0 X X No action. 1 0 1 X X START transmitted on serial bus followed by sequence stored in buffer. Active (reset, load TRANCONFIG, SLATABLE, DATA, STA = 1 1 0 X 0 X No change; cannot write STA while active.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior …continued Channel state (initialization steps) Next write action by host FRAMECNT TE Results STA STO STOSEQ Trigger Loop active (reset, load X TRANCONFIG, SLATABLE, X DATA, STA = 1) 1 X 0 0 No action. 1 X 0 1 Channel will go immediately to the inactive state and SD and FLD bits will be set.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller FE - Frame Error bit: This bit indicates that the time required to send the sequence exceeds the refresh rate programmed in the REFRATE register or the time between trigger ticks. Solving frame errors include programming longer refresh rates, speeding up the bus frequency, shortening the amount of bytes sent/received in the sequence, or increasing the time between trigger ticks.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 8. Error detection operation/behavior Channel state AR (MODE register) DAE CLE SSE Active or idle X 0 0 1 Interrupt set, if a transaction is active it will be immediately aborted and no further action taken by controller. Host to re-initialize bus (i.e., force a bus recovery), reset slaves, or take other appropriate recovery action. After bus is recovered, host to re-start transaction.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 9. INTMSK - Interrupt mask register bit description …continued Address: Channel 0 = C2h. Bit Symbol Description 3:1 - reserved 0 FEMSK Frame Error Mask. A frame error interrupt will not be generated. Remark: Use caution and good judgement when using this mask. Unexpected/erratic behavior may result in the slave devices. 7.5.1.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.1.6 TRANCONFIG — Transaction configuration register The TRANCONFIG register is an 8-bit  65 register set that makes up a table that contains the number of transactions that will be executed in a sequence and the number of data bytes involved in the transaction. The first byte of the register is the Transaction Count register. The remaining 64 registers are the Transaction Length registers. Table 12.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller To return to the data location pointed by the contents of the TRANSEL and TRANOFS register after read or write access to the DATA register, set the AIPTRRST (auto-increment pointer reset) bit in the control register. To return to the first DATA register location in the buffer set the TRANSEL to 00h. Table 15. DATA - Data register bit description Address: Channel 0 = C5h. 7.5.1.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.1.9 TRANOFS — Transaction data buffer byte select register In conjunction with the TRANSEL register, the TRANOFS register is used to select the pointer to a specific byte in a transaction in the data buffer. This allows the user to read or re-write a specific data byte of a specific slave without having to read/re-write the entire data buffer.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller If the FRAMECNT is 01h, it is defined as the default state and the sequence stored in the buffer will be sent once and a STOP will be sent at the end of the sequence. If the FRAMECNT is greater than 01h, the sequence stored in the buffer will loop FRAMECNT times and a STOP will be sent at the end of each sequence. Remark: The FRAMECNT can only be set to loop on the sequence stored in the buffer. 7.5.1.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Fast-mode Plus (Fm+) is the default selected mode at power-up or after reset. The clock is derived from the internal PLL frequency which is set at 156 MHz (13  OSC clock). Given a 1 % accuracy on the internal clock, the worst case TPLL is 1 1 ---------------------------------------- = ------------------------------- = 6.347 ns . 12.12 MHz  13 157.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 24. Typical SCL frequencies …continued Data shown under following conditions: Pull-up resistor RPU = 500 ; bus capacitance Cb = ~170 pF. Desired frequency (kHz) Actual frequency (kHz) SCLL SCLH 400 398.4 58 39 350 348.7 66 45 300 298.2 78 52 250 250.2 93 62 200 198.0 117 79 150 150.1 155 104 100 100.0 233 156 1000 999.0 90 63 900 900.0 100 70 800 798.3 113 79 700 698.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.1.14 MODE — I2C-bus mode register MODE is a read/write register. It contains the control bits that select the bus recovery options, and the correct timing parameters. Timing parameters involved with AC[1:0] are tBUF, tHD;STA, tSU;STA, tSU;STO, tHIGH, tLOW. The auto recovery and bus recovery bits are contained in this register. They control the bus recovery sequence as defined in Section 8.5.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 26. I2C-bus frequency (kHz)[1] Scale factor AC[1:0] Mode 100 8 00 Standard 400 4 01 Fast 1000 1 10 Fast-mode Plus - - 11 reserved [1] 7.5.1.15 I2C-bus mode selection example Using the formula 1 f SCL = ----------------------------------------------------------------------------------------T PLL   SCLL + SCLH   sf  + t r + t f TIMEOUT — Time-out register TIMEOUT is an 8-bit read/write register.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.1.16 PRESET — I2C-bus channel parallel software reset register Table 28. PRESET - I2C-bus channel parallel software reset register bit description Address: Channel 0 = CFh. Bit Symbol 7:0 PRESET[7:0] Read/Write register used during an I2C-bus channel parallel reset command. Description PRESET is an 8-bit write-only register.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller When the DATA register is loaded with data that goes beyond the capacity of the buffer, the bytes that go over the buffer size will be ignored and a Buffer Error (BE) will be generated. Special case: The BE interrupt is cleared by reading the CTRLSTATUS register. All other interrupts are cleared by reading the respective CHSTATUS register. SD FLD WE RE CH0INTP (Fm+) DAE CLE SSE FE Fig 4.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 7.5.2.3 DEVICE_ID — Device ID The DEVICE_ID register stores the bus controller part number so it can be identified on the parallel bus. Table 31. DEVICE_ID - Device ID register bit description Address: F6h. Bit Symbol Description 7 U/A Selects PCU or PCA device. 1 = PCU96xx 0 = PCA96xx 6:0 7.5.2.4 BCD BCD (Binary Coded Decimal) code of the ending 2 digits for ID. Range is 00h to 79h. The code for the PCA9661 is 61h.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller CE RD DATA FFh FFh 00h ready initializing 002aag095 Fig 6. During initialization, CE must transition with RD at each read operation ADDR read address X read address Y read address Z CE RD DATA address X address Y address Z 002aag096 Fig 7.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 8. PCA9661 operation The PCA9661 is designed to efficiently transmit and receive large amounts of data on a single master bus.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller In Figure 9, circles are used to indicate when a bit is set in the CHSTATUS register. A channel interrupt is not requested when CHSTATUS = 00h and the INT pin is not asserted when the interrupt is masked (see Section 7.5.2.2). For a successful sequence execution, all three components mentioned above must exist in the memory and must be correctly set up.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA9661 Product data sheet transactions with WEMSK and REMSK = 0 S SLA 0 W A A 01h
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 8.2 Read transactions Many I2C-bus slave devices need a command or register offset to setup a read operation. In this case, a read transaction is actually a multi-part transaction consisting of a write transaction followed by a read transaction. This is done by setting the transactions in that order when programming the sequence.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Once the FRAMECNT values is reached, the FLD bit in the CHSTATUS register is set and no further transactions will be executed and the channel will go to the idle state. The FLD interrupt can be masked with the FLDMSK bit in the CTRLINTMSK register. The host can poll the CTRLSTATUS register to check if the channel is active (looping) or if it is idle. For indefinite or long term looping the host can do the following: 1.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 8.5 Bus errors (Fm+ channel only) Bus errors are a rare occurrence in a well designed I2C-bus system. The PCA9661 has a robust error detection mechanism that detects hang-ups such as if SDA or SCL is pulled LOW by an external source, or if an illegal START or STOP condition appears on the bus. 8.5.1 I2C-bus obstructed by a LOW level on SDA (DAE) An I2C-bus hang-up occurs if SDA is pulled LOW by an uncontrolled source (e.g.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller line released by slave, bus recovered S SDA line line driven by master P line held LOW by slave 1 2 3 4 5 6 7 8 9 SCL line fault detected at START 9 clocks driven by master START condition STOP condition 002aaf621 Fig 11. Recovering from a bus obstruction caused by a LOW level on SDA (AR = 1) 8.5.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller The complete power-up initialization phase takes trst to be performed. During this time, writes to the PCA9661 through the parallel port are ignored. However, the parallel port can be read. This allows the device connected to the parallel port of the PCA9661 to poll the CTRLRDY register. 8.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 8.8 Channel reset In addition to the above chip reset options, each channel can be individually reset by programming the PRESET register for that channel as described in Figure 13. The channel will reset to its default power-up state. The host must write to the PRESET register of the target channel in two successive parallel bus writes to the bus controller. The first byte is A5h and the second byte is 5Ah.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 8.9 I2C-bus timing diagrams The diagrams Figure 14 and Figure 15 illustrate typical timing diagrams for the PCA9661. SCL SDA INT 7-bit address(1) first byte(1) R/W = 0 START condition ACK interrupt (after STOP) n byte(1) ACK ACK STOP condition 002aaf301 from slave receiver PCA9661 writes data to slave.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller SDA SCL PCA9661 MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER I2C-BUS MULTIPLEXER SLAVE TRANSMITTER/ RECEIVER 002aag309 Fig 18. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 10. JTAG port The PCA9661 has a JTAG IEEE 1149.1 compliant port. All signals (TDI, TMS, TCK, TRST and TDO) are accessible. Only EXTEST functions are enabled, for example to conduct board-level continuity tests. Device debug/emulation functionality such as INTEST commands are not supported. The JTAG port is used for boundary scan testing (i.e., opens/shorts) during PCB manufacturing.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 11. Application design-in information VDD address bus VDD(IO) VDD VDD(IO) A0 A1 SCL0 A2 A3 SDA0 A4 A5 PCA9661 A6 A7 CE 80C51 ALE DECODER SLAVE INT SLAVE RESET 8 D0 to D7 RD WR VDD TRIG VDD INT RESET VSS VSS 002aag292 Fig 20. Application diagram using the 80C51 11.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 11.2 Add I2C-bus port As shown in Figure 21, the PCA9661 converts 8-bits of parallel data into a single master capable I2C-bus port for microcontrollers, microprocessors, custom ASICs, DSPs, etc., that need to interface with I2C-bus or SMBus components. control signals MICROCONTROLLER, MICROPROCESSOR, OR ASIC SDA0 SCL0 PCA9661 8 bits data 002aae820 Fig 21. Adding I2C-bus port application 11.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 12. Limiting values Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage VDD(IO) input/output supply voltage power supply reference for I2C-bus I/O pins VI input voltage parallel bus interface I2C-bus pins [1] Min Max Unit 0.3 +4.6 V 0.3 +7.0 V 0.3 +4.6 V 0.3 +7.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Table 35. Static characteristics …continued VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 0 - 0.3VDD V 0.7VDD - 3.6 V 0.1VDD - - V Input RESET VIL LOW-level input voltage [1] VIH HIGH-level input voltage Vhys hysteresis voltage IL leakage current input; VI = 0 V or 3.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 14. Dynamic characteristics Table 36. Dynamic characteristics (3.3 volt)[1][2][3] VDD = 3.3 V  0.3 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Initialization timing tinit(po) power-on initialization time VDD  3.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller A0 to A7 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(RDL) tw(RDH) RD td(QZ) td(DV) D0 to D7 (read) float not valid valid float 002aaf458 Fig 23. Bus timing (read cycle) A0 to A7 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(WRL) tw(WRH) WR tsu(Q) D0 to D7 (write) th(Q) valid 002aaf459 Fig 24.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller VI RD, CE input VM VSS VM t d(QLZ) t d(QZL) VDD Dn output LOW-to-float float-to-LOW VM VX VOL t d(QZH) t d(QHZ) Dn output HIGH-to-float float-to-HIGH VOH VY VM VSS outputs enabled outputs floating outputs enabled 002aaf172 VM = 1.5 V VX = VOL + 0.2 V VY = VOH  0.2 V VOL and VOH are typical output voltage drops that occur with the output load. Fig 25.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA9661 Product data sheet Table 37.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller SDA tLOW tf tSU;DAT tr tHD;STA tSP tf tBUF tr SCL tHIGH tSU;STA tHD;DAT tHD;STA S tSU;STO Sr P S 002aab271 Fig 26. Definition of timing on the I2C-bus protocol START condition (S) tSU;STA bit 7 MSB tLOW bit 6 tHIGH bit n acknowledge (A) bit 0 STOP condition (P) 1/f SCL SCL tBUF tf tr SDA tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aac696 Rise and fall times refer to VIL and VIH. Fig 27.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 15. Test information VDD PULSE GENERATOR VI RL 500 Ω VO VDD × 2 open VSS DUT CL 50 pF RT RL 500 Ω 002aac694 Test data are given in Table 38. RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance ZO of the pulse generators. Fig 28. Test circuitry for switching times Table 38.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 16. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 42.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 20. Revision history Table 43. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9661 v.1 20110804 Product data sheet - - PCA9661 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 4 August 2011 © NXP B.V. 2011. All rights reserved.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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PCA9661 NXP Semiconductors Parallel bus to 1 channel Fm+ I2C-bus controller 22 23 Contact information. . . . . . . . . . . . . . . . . . . . . 61 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.