Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLinear ICsPCA9663B,118

1. General description

The PCA9663 is an advanced single master mode I

C-bus controller. It is a fourth

generation bus controller designed for data intensive I

C-bus data transfers. It has three

independent I

C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus

(Fm+) open-drain topology. Each channel has a generous 4352 byte data buffer which

makes the PCA9663 the ideal companion to any CPU that needs to transmit and receive

large amounts of serial data.

The PCA9663 is a 8-bit parallel-bus to I

C-bus protocol converter. Each channel can be

configured to communicate with up to 64 slaves in one serial sequence with no

intervention from the CPU. The controller also has a sequence loop control feature that

allows it to automatically retransmit a stored sequence.

Its onboard oscillator and PLL allow the controller to generate the clocks for the I

C-bus

and for the interval timer used in sequence looping. This feature greatly reduces CPU

overhead when data refresh is required in fault tolerant applications.

An external trigger input allows data synchronization with external everts. The trigger

signal controls the rate at which a stored sequence is re-transmitted over the I

C-bus.

Error reporting is handled at the transaction level, channel level and controller level with a

simple interrupt tree and interrupt masks allow further customization of interrupt

management.

The controller and parallel bus interfaces run at 3.3 V and the I

C-bus I/Os are 5 V

tolerant with logic levels referenced to a dedicated V

DD(IO)

input pin with a range of 3.0 V

to 5.5 V.

2. Features and benefits

 Parallel-bus to I

C-bus protocol converter and interface

 1 Mbit/s and up to 30 mA SCL/SDA I

Fast-mode Plus (Fm+) capability

 Internal oscillator trimmed to 1 % accuracy reduces external components

 Individual 4352-byte buffers for the Fm+ channels for a total of 13056 bytes of buffer

space

 Three levels of reset: individual software reset, global software reset, global hardware

RESET

 Communicates with up to 64 slaves on each channel in one serial sequence

 Sequence looping with interval timer

 Supports SCL clock stretching

 JTAG port available for boundary scan testing during board manufacturing process

 Trigger input synchronizes serial communication exactly with external events

PCA9663

Parallel bus to 3 channel Fm+ I

C-bus controller

Rev. 1 — 6 June 2011 Product data sheet

Summary of content (66 pages)

PAGE 1
PCA9663 Parallel bus to 3 channel Fm+ I2C-bus controller Rev. 1 — 6 June 2011 Product data sheet 1. General description The PCA9663 is an advanced single master mode I2C-bus controller. It is a fourth generation bus controller designed for data intensive I2C-bus data transfers. It has three independent I2C-bus channels with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller       Maskable interrupts Fast-mode Plus I2C-bus capable and compatible with SMBus Operating supply voltage: 3.0 V to 3.6 V (device and host interface) I2C-bus I/O supply voltage: 3.0 V to 5.5 V Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA ESD protection exceeds 8000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-C101  Packages offered: LQFP48 3.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 5.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 6. Pinning information 37 D0 39 VSS 38 D1 40 VDD 41 D2 42 D3 44 VDD 43 VSS 45 D4 46 D5 D6 1 36 RESET D7 2 35 VSS A0 3 34 TRIG A1 4 33 CE A2 5 32 RD A3 6 VDD 7 VSS 8 29 VSS A4 9 28 SCL0 A5 10 27 SDA0 A6 11 26 SCL1 A7 12 25 SDA1 31 WR VDD(IO) 24 VSS(IO) 23 SCL2 22 30 VDD SDA2 21 INT 20 VSS 19 VDD 18 TDO 17 TDI 16 TCK 15 TMS 14 PCA9663B TRST 13 Fig 2. 47 VSS 48 VDD 6.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 2. Pin description …continued Symbol Pin Type Description TRST 13 I JTAG test reset input. For normal operation, hold LOW (VSS). TMS 14 I JTAG test mode select input. For normal operation, hold HIGH (VDD). TCK 15 I JTAG test clock input. For normal operation, hold HIGH (VDD). TDI 16 I JTAG test data in input. For normal operation, hold HIGH (VDD). TDO 17 O JTAG test data out output.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 2. Pin description …continued Symbol Pin Type Description VDD 7, 18, 30, 40, 44, 48 power Power supply: 3.0 V to 3.6 V. All VDD pins should be connected together externally. VSS 8, 19, 29, power 35, 39, 43, 47 Supply ground. All VSS pins must be tied together externally. 7. Functional description 7.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller DATA until the entire sequence is loaded. If the transaction is a read transaction, the host must write a dummy byte (i.e., FFh) for each expected serial read byte to reserve the memory space in the buffer for the transaction. Care should be taken so as to not overflow the buffer with excessive read/write commands. In the event of an overflow, represented by the BE bit in the CTRLSTATUS register, will be set to logic 1.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Remark: Note that the bytes required to store the 30 slave addresses are not included in the calculation since they are stored in the SLATABLE register. 7.4 Error reporting and handling In case of any transaction error conditions, the device will load the transaction error status in the STATUSx_[n], generate an interrupt, if unmasked, by pulling down the INT pin and update the CHSTATUS and CTRLSTATUS registers.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1 Channel registers 7.5.1.1 STATUS0_[n], STATUS1_[n], STATUS2_[n] — Transaction status registers STATUS0_[n], STATUS1_[n], and STATUS2_[n] are 8-bit  64 read-only registers that provide status information for a given transaction. Only the 5 lower bits are used; the top bits will always read 0. When some of these bits are set, a channel interrupt is requested (the INT pin is asserted LOW).
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller After STA is set: STATUSx_[0] = 2 STATUSx_[1] = 1 STATUSx_[2] = 1 STATUSx_[3] = 0 : Since there is no timing requirement in setting the STA bit after the initialization, the device will update the first status when the STA bit is set and will always go from 0 to 2 (Idle to Transaction active). 7.5.1.2 CONTROL — Control register CONTROL is an 8-bit register.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 5. CONTROL - Control register bit description …continued Address: Channel 0 = C0h; Channel 1 = D0h; Channel 2 = E0h. Legend: * reset value Bit Symbol Access 4 TP R/W 3 TE Value Description Trigger polarity bit. Cannot be changed while channel is active. 1 Trigger will be detected on a falling edge. 0 Trigger will be detected on a rising edge.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior Channel state (initialization steps) Next write action by host Results FRAMECNT TE STA STO STOSEQ Idle (reset, TRANCONFIG, SLATABLE, DATA, STA = 0) 1 0 0 X X No action. 1 0 1 X X START transmitted on serial bus followed by sequence stored in buffer.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 6. CONTROL register bits STA, STO, STOSEQ operation/behavior …continued Channel state (initialization steps) Next write action by host FRAMECNT TE Results STA STO STOSEQ Trigger Loop active (reset, load X TRANCONFIG, SLATABLE, X DATA, STA = 1) 1 X 0 0 No action. 1 X 0 1 Channel will go immediately to the inactive state and SD and FLD bits will be set.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller FE - Frame Error bit: This bit indicates that the time required to send the sequence exceeds the refresh rate programmed in the REFRATE register or the time between trigger ticks. Solving frame errors include programming longer refresh rates, speeding up the bus frequency, shortening the amount of bytes sent/received in the sequence, or increasing the time between trigger ticks.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 8. Error detection operation/behavior Channel state AR (MODE register) Error detected (CHSTATUS DAE CLE SSE Active or idle X 0 0 1 Interrupt set, if a transaction is active it will be immediately aborted and no further action taken by controller. Host to re-initialize bus (i.e., force a bus recovery), reset slaves, or take other appropriate recovery action. After bus is recovered, host to re-start transaction.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1.5 SLATABLE — Slave address table register SLATABLE is an 8-bit  64 register set that makes up a table that stores the slave address for each transaction in the sequence. The table is loaded by using an auto-increment pointer that is not user-accessible. To reset the pointer, the AIPTRRST bit must be set in the CONTROL register. The slave addresses in the SLATABLE register are stored with a zero-based (N  1) index.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1.6 TRANCONFIG — Transaction configuration register The TRANCONFIG register is an 8-bit  65 register set that makes up a table that contains the number of transactions that will be executed in a sequence and the number of data bytes involved in the transaction. The first byte of the register is the Transaction Count register. The remaining 64 registers are the Transaction Length registers. Table 12.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller To return to the data location pointed by the contents of the TRANSEL and TRANOFS register after read or write access to the DATA register, set the AIPTRRST (auto-increment pointer reset) bit in the control register. To return to the first DATA register location in the buffer set the TRANSEL to 00h. Table 15. DATA - Data register bit description Address: Channel 0 = C5h; Channel 1 = D5h; Channel 2 = E5h. 7.5.1.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1.9 TRANOFS — Transaction data buffer byte select register In conjunction with the TRANSEL register, the TRANOFS register is used to select the pointer to a specific byte in a transaction in the data buffer. This allows the user to read or re-write a specific data byte of a specific slave without having to read/re-write the entire data buffer.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller If the FRAMECNT is 01h, it is defined as the default state and the sequence stored in the buffer will be sent once and a STOP will be sent at the end of the sequence. If the FRAMECNT is greater than 01h, the sequence stored in the buffer will loop FRAMECNT times and a STOP will be sent at the end of each sequence. Remark: The FRAMECNT can only be set to loop on the sequence stored in the buffer. 7.5.1.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller The clock is derived from the internal PLL frequency which is set at 156 MHz (13 OSC clock). Given a 1 % accuracy on the internal clock, the worst case TPLL is 1 1 ---------------------------------------- = ------------------------------- = 6.347 ns . 12.12 MHz  13 157.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 24. Typical SCL frequencies …continued Data shown under following conditions: Pull-up resistor RPU = 500 ; bus capacitance Cb = ~170 pF. Desired frequency (kHz) Actual frequency (kHz) SCLL SCLH 400 398.4 58 39 350 348.7 66 45 300 298.2 78 52 250 250.2 93 62 200 198.0 117 79 150 150.1 155 104 100 100.0 233 156 1000 999.0 90 63 900 900.0 100 70 800 798.3 113 79 700 698.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1.14 MODE — I2C-bus mode register MODE is a read/write register. It contains the control bits that select the bus recovery options, and the correct timing parameters. Timing parameters involved with AC[1:0] are tBUF, tHD;STA, tSU;STA, tSU;STO, tHIGH, tLOW. The auto recovery and bus recovery bits are contained in this register. They control the bus recovery sequence as defined in Section 8.5.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 26. 7.5.1.15 I2C-bus mode selection example[1] SCLL (decimal) SCLH (decimal) I2C-bus frequency Scale (kHz)[2] factor AC[1:0] Mode 118 79 100 8 00 Standard 59 39 400 4 01 Fast 94 63 1000 1 10 Fast-mode Plus - - - - 11 reserved [1] SCLL and SCLH values in the table also represents the minimum values that can be used for the corresponding I2C-bus mode.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.1.16 PRESET — I2C-bus channel parallel software reset register Table 28. PRESET - I2C-bus channel parallel software reset register bit description Address: Channel 0 = CFh; Channel 1 = DFh; Channel 2 = EFh. Bit Symbol 7:0 PRESET[7:0] Write-only register used during an I2C-bus channel parallel reset command. Description PRESET is an 8-bit write-only register.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller The buffer error may occur when a data location is being read or written to that has not previously been configured by the TRANCONFIG register. The buffer error can occur on a parallel data write or read beyond the buffer capacity, or setting the TRANSEL and TRANOFS pointers beyond the buffer boundary.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.2.2 CTRLINTMSK — Control Interrupt mask register The CTRLINTMSK masks all interrupts generated by the masked channel. This allows the host MCU to complete other operations before servicing the interrupt without being interrupted by the same channel. Table 30. CTRLINTMSK - Control interrupt mask register bit description Address: F1h. Bit Symbol Description 7 BEMSK Buffer Error Mask.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller SD SDMSK WE WEMSK RE REMSK CH0 interrupt sources and masks FE FEMSK CH0MSK FLD FLDMSK DAE CLE SSE SD SDMSK WE WEMSK RE REMSK CH1 interrupt sources and masks FE FEMSK CH1MSK FLD FLDMSK to INT pin BE BEMSK DAE CLE SSE SD SDMSK WE WEMSK RE REMSK CH2 interrupt sources and masks FE FEMSK CH2MSK FLD FLDMSK DAE CLE SSE Fig 5. 7.5.2.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 7.5.2.4 CTRLPRESET — Parallel software reset register Table 32. CTRLPRESET - Parallel software reset register bit description Address: F7h. Bit Symbol 7:0 CTRLPRESET[7:0] Write-only register used during a device parallel reset command. Description CTRLPRESET is an 8-bit write-only register. Programming the CTRLPRESET register allows the user to reset the PCA9663 under software control.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller ADDR read address X read address Y read address Z CE RD DATA address X address Y address Z 002aag096 Fig 7. During normal operation, CE may remain LOW while RD transitions during multiple reads ADDR write address X write address Y write address Z CE WR DATA data X data Y data Z 002aag097 Fig 8. During normal operation, CE may remain LOW while WR transitions during multiple writes 8.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Transmitter or a Master Receiver according to the direction bits specified in the SLATABLE. The host has the ability to retrieve stored serial data as soon as a read transaction is done, while the controller carries on the remaining transactions in the sequence. 8.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller When the interrupts are unmasked, a NACK on slave address or data (in a write cycle) will terminate the serial transfer, generate a STOP, and the INT pin will be asserted. The host can read the CTRLSTATUS (Controller status register) to determine which channel generated the interrupt, then it can read the CHSTATUS register of the channel and the STATUSx_[n] to determine which slave address caused the error.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 8.2 Read transactions Many I2C-bus slave devices need a command or register offset to setup a read operation. In this case, a read transaction is actually a multi-part transaction consisting of a write transaction followed by a read transaction. This is done by setting the transactions in that order when programming the sequence.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Once the FRAMECNT values is reached, the FLD bit in the CHSTATUS register is set and no further transactions will be executed and the channel will go to the idle state. The FLD interrupt can be masked with the FLDMSK bit in the CTRLINTMSK register. The host can poll the CTRLSTATUS register to check if the channel is active (looping) or if it is idle. For indefinite or long term looping the host can do the following: 1.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 8.5 Bus errors Bus errors are a rare occurrence in a well designed I2C-bus system. The PCA9663 has a robust error detection mechanism that detects hang-ups such as if SDA or SCL is pulled LOW by an external source, or if an illegal START or STOP condition appears on the bus. 8.5.1 I2C-bus obstructed by a LOW level on SDA (DAE) An I2C-bus hang-up occurs if SDA is pulled LOW by an uncontrolled source (e.g.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller line released by slave, bus recovered S SDA line line driven by master P line held LOW by slave 1 2 3 4 5 6 7 8 9 SCL line fault detected at START 9 clocks driven by master START condition STOP condition 002aaf621 Fig 11. Recovering from a bus obstruction caused by a LOW level on SDA (AR = 1) 8.5.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 8.6 Power-on reset When power is applied to VDD, an internal Power-On Reset holds the PCA9663 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9663 goes to the power-up initialization phase where the following operations are performed: 1. The oscillator and PLL will be re-initialized. 2. Internal register initialization is performed. 3. The memory space will be zeroed out.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 8.8 Channel reset In addition to the above chip reset options, each channel can be individually reset by programming the PRESET register for that channel as described in Figure 13. The channel will reset to its default power-up state. The host must write to the PRESET register of the target channel in two successive parallel bus writes to the bus controller. The first byte is A5h and the second byte is 5Ah.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 8.9 I2C-bus timing diagrams The diagrams Figure 14 and Figure 15 illustrate typical timing diagrams for the PCA9663. SCL SDA INT 7-bit address(1) first byte(1) R/W = 0 START condition ACK interrupt (after STOP) n byte(1) ACK ACK STOP condition 002aaf301 from slave receiver PCA9663 writes data to slave.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller SDA SCL PCA9663 MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER I2C-BUS MULTIPLEXER SLAVE TRANSMITTER/ RECEIVER 002aaf694 Fig 18. System configuration 9.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 10. JTAG port The PCA9663 has a JTAG IEEE 1149.1 compliant port. All signals (TDI, TMS, TCK, TRSTN and TDO) are accessible. Only EXTEST functions are enabled, for example to conduct board-level continuity tests. Device debug/emulation functionality such as INTEST commands are not supported. The JTAG port is used for boundary scan testing (i.e., opens/shorts) during PCB manufacturing.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 11. Application design-in information VDD address bus VDD(IO) VDD VDD(IO) A0 A1 SCL0 A2 A3 SDA0 A4 A5 PCA9663 A6 A7 CE SCL1 SDA1 D0 to D7 80C51 ALE DECODER 8 SLAVE INT SLAVE RD WR VDD SLAVE RESET SCL2 SDA2 VDD INT SLAVE RESET VSS VSS 002aae936 Fig 20. Application diagram using the 80C51 11.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 11.2 Add I2C-bus port As shown in Figure 21, the PCA9663 converts 8-bits of parallel data into a single master capable I2C-bus port for microcontrollers, microprocessors, custom ASICs, DSPs, etc., that need to interface with I2C-bus or SMBus components. SDA0 SCL0 control signals MICROCONTROLLER, MICROPROCESSOR, OR ASIC SDA1 SCL1 PCA9663 8 bits data SDA2 SCL2 002aae937 Fig 21. Adding I2C-bus port application 11.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 12. Limiting values Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions VDD supply voltage VDD(IO) input/output supply voltage power supply reference for I2C-bus I/O pins VI input voltage parallel bus interface I2C-bus [1] pins Min Max Unit 0.3 +4.6 V 0.3 +7.0 V 0.3 +4.6 V 0.3 +7.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Table 35. Static characteristics …continued VDD = 3.0 V to 3.6 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 0 - 0.3VDD V 0.7VDD - 3.6 V 0.1VDD - - V Inputs WR, RD, A0 to A7, CE, TRIG LOW-level input voltage VIL [1] VIH HIGH-level input voltage Vhys hysteresis voltage IL leakage current input; VI = 0 V or 3.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 14. Dynamic characteristics Table 36. Dynamic characteristics (3.3 volt)[1][2][3] VDD = 3.3 V  0.3 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Initialization timing tinit(po) power-on initialization time VDD = 3.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller A0 to A7 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(RDL) tw(RDH) RD td(QZ) td(DV) D0 to D7 (read) float not valid valid float 002aaf458 Fig 23. Bus timing (read cycle) A0 to A7 tsu(A) th(A) CE tsu(CE_N) th(CE_N) tw(WRL) tw(WRH) WR tsu(Q) D0 to D7 (write) th(Q) valid 002aaf459 Fig 24.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller VI RD, CE input VM VSS VM t d(QLZ) t d(QZL) VDD Dn output LOW-to-float float-to-LOW VM VX VOL t d(QZH) t d(QHZ) Dn output HIGH-to-float float-to-HIGH VOH VY VM VSS outputs enabled outputs floating outputs enabled 002aaf172 VM = 1.5 V VX = VOL + 0.2 V VY = VOH  0.2 V VOL and VOH are typical output voltage drops that occur with the output load. Fig 25.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors PCA9663 Product data sheet Table 37.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller SDA tLOW tf tSU;DAT tr tHD;STA tSP tf tBUF tr SCL tHIGH tSU;STA tHD;DAT tHD;STA S tSU;STO Sr P S 002aab271 Fig 26. Definition of timing on the I2C-bus protocol START condition (S) tSU;STA bit 7 MSB tLOW bit 6 tHIGH bit n acknowledge (A) bit 0 STOP condition (P) 1/f SCL SCL tBUF tf tr SDA tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aac696 Rise and fall times refer to VIL and VIH. Fig 27.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 15. Test information VDD PULSE GENERATOR VI VDD × 2 open VSS RL 500 Ω VO DUT CL 50 pF RT RL 500 Ω 002aac694 Test data are given in Table 38. RL = load resistance. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance ZO of the pulse generators. Fig 28. Test circuitry for switching times Table 38.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 16. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 1 detail X 12 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 31. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 42.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements.
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.3.2 7.4 7.5 7.5.1 7.5.1.1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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PCA9663 NXP Semiconductors Parallel bus to 3 channel Fm+ I2C-bus controller 22 23 Contact information. . . . . . . . . . . . . . . . . . . . . 64 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. All rights reserved. For more information, please visit: http://www.nxp.