Datasheet

Product data sheet Rev. 6 — 15 July 2013 35 of 64

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

9. 3-line serial interface

Data transfer to and from the device is made via a 3-wire SPI-bus (see Table 42). The

data lines for input and output are split. The data input and output lines can be connected

together to facilitate a bidirectional data bus. The chip enable signal is used to identify the

transmitted data. Each data transfer is a byte, with the Most Significant Bit (MSB) sent first

(see Figure 24

The transmission is controlled by the active HIGH chip enable signal CE. The first byte

transmitted is the command byte. Subsequent bytes will be either data to be written or

data to be read. Data is sampled on the rising edge of the clock and transferred internally

on the falling edge.

The command byte defines the address of the first register to be accessed and the

read/write mode. The address counter will auto increment after every access and will

rollover to zero after the last register is accessed. The read/write

bit (R/W) defines if the

following bytes will be read or write information.

Table 42. Serial interface

Symbol Function Description

CE chip enable input when LOW, the interface is reset; pull-down resistor

included; active input may be higher than V

, but may not

be wired permanently HIGH

SCL serial clock input when CE is LOW, this input may float; input may be higher

than V

SDI serial data input when CE is LOW, input may float; input may be higher than

; input data is sampled on the rising edge of SCL

SDO serial data output push-pull output; drives from V

to V

; output data is

changed on the falling edge of SCL; will be high-Z when not

driving; may be connected directly to SDI

Fig 23. SDI, SDO configurations

Fig 24. Data transfer overview

001aai560

SDI

two wire mode

SDO

SDI

single wire mode

SDO

001aaf914

COMMANDdata bus

chip enable

DATA DATADATA