PCF8536 Universal LCD driver for low multiplex rates including a 6 channel PWM generator Rev. 2 — 21 February 2012 Product data sheet 1. General description The PCF8536 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any multiplexed LCD containing up to eight backplanes, up to 44 segments, and up to 320 elements.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 320 segments driven allowing: up to 40 7-segment alphanumeric characters up to 20 14-segment alphanumeric characters any graphics of up to 320 elements Manufactured in silicon gate CMOS process 3. Applications White goods and consumer products 4. Ordering information Table 1.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 6.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator VDD BP4 to BP7/ S40 to S43 BP0 to BP3 S6 to S39 S0/GP0 to S5/GP5 VLCD BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY SEGMENT OUTPUTS GPO/PWM GENERATOR DISPLAY REGISTER VSS OSCCLK RESET SCL SDI LCD BIAS GENERATOR OSCILLATOR AND CLOCK SELECTION PRESCALER AND TIMING POWER-ON RESET DISPLAY RAM AND PWM REGISTERS PCF8536BT COMMAND DECODER WRITE DATA CONTROL DATA POINTER, AUTO INCREMENT SPI-BUS CON
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PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 7.2 Pin description Table 3.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8. Functional description The PCF8536 is a versatile peripheral device designed to interface any microcontroller to a wide variety of LCDs and 6 backlight LEDs. It can directly drive any multiplexed LCD containing up to eight backplanes and up to 44 segments. 8.1 Commands of PCF8536 The PCF8536 is controlled by 15 commands, which are defined in Table 4.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.1.2 Command: OTP-refresh During production and testing of the device, each IC is calibrated to achieve the specified accuracy of the frame frequency. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. The device reads these cells every time the OTP-refresh command is sent. This instruction has to be sent after a reset has been made and before the display is enabled.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.1.4 Command: mode-settings Table 8. Bit Symbol Value Description 7 to 4 - 0101 fixed value 3 BPS 2 1 0 8.1.4.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator BP0 12 S32 12 BP1 13 S33 13 BP2 14 S34 14 BP3 15 S35 15 BP4/S43 16 S36 16 BP5/S42 17 S37 17 BP6/S41 18 39 S39 S38 18 39 BP0 BP7/S40 19 38 S38 S39 19 38 BP1 S20 20 37 S37 S20 20 37 BP2 S21 21 36 S36 S21 21 36 BP3 S22 22 35 S35 S22 22 35 BP4/S43 S23 23 34 S34 S23 23 34 BP5/S42 S24 24 33 S33 S24 24 33 BP6/S41 S25 25 32 S32 S25 25 32 BP7/S40 S26 26 31 S31 S26 26 31 S31 S2
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 9.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator • A clock signal must always be supplied to the device when the display is active. Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. It is recommended to disable the display first and afterwards to remove the clock signal. 8.1.4.4 Display enable The display enable bit (E) is used to enable and disable the display.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator COE (1) EFR (2) 0 OSCCLK pin 1 Internal oscillator 230 kHz Programmable divider 0 OSC LCD frame frequency selection, q 0 (4) 9.6 kHz (3) Programmable divider 1 LCD waveform generator 1 PWM waveform generator PWM frame frequency selection, p 013aaa448 (1) Can only be used with the internal oscillator (OSC = 0). (2) Can only be used with an external oscillator (OSC = 1).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 13. Internal oscillator on/off table PD OSC PWM EFR Internal oscillator state[1] power-down n.a. n.a. n.a. off power-up internal oscillator n.a. n.a. on external oscillator off n.a. off on 9.6 kHz on[2] on 230 kHz off [1] When RESET is active, the internal oscillator is off. [2] Special case. The PWM generator needs 230 kHz and must be enabled when PWM is enabled.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Remark: If an external clock is used, then this clock signal must always be supplied to the device when the display is on. Removing the clock may freeze the LCD in a DC state which will damage the LCD material. 8.1.5.2 Timing and frame frequency The timing of the PCF8536 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 17. GPMO mode definition GPM0[1:0] to GPM5[1:0] Mode Description 00[1], LCD output is an LCD segment 01 10 static output is static GPO 11 PWM output is PWM GPO [1] Default value. 8.1.7 Command: set-MUX-mode The multiplex drive mode is configured with the bits described in Table 18. Table 18.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation 2: f clk ext f fr LCD = ---------------48 q (2) where q is the frequency divide factor (see Table 21). Remark: fclk(ext) is the external input clock frequency to pin OSCCLK. When the internal oscillator is used, the intermediate frequency may be output on the OSCCLK pin. Its frequency is given in Table 21. Table 21.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.1.10 Command: frame-frequency-PWM With the frame-frequency-PWM command, the frame frequency for the PWM signal can be set. The PWM system requires a clock of 230 kHz either internally generated or externally supplied. Using a slower clock may result in visible flickering of LEDs driven with the PWM signal.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Intensity of visible flickering In general, the higher the PWM frame frequency, the less flickering will be visible Flickering is most visible when fPWM and ffr(LCD) are within 10 Hz of each other Flickering is also visible at multiples of the fundamental frequency; however, the visibility is lower Flickering will not be visible when fPWM and ffr(LCD) are more than 50 Hz apart f1 2f1 This will repeat for 3f1,
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.1.12 Command: load-data-pointer-LCD The load-data-pointer-LCD command defines the start address of the display RAM. The data pointer is auto incremented after each RAM write. The size of the display RAM is dependent on the current multiplex drive mode setting, see Table 25. Table 25.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.1.15 Command: write-PWM-data This command will initiate the transfer of data to the PWM registers. Data will be written into the address defined by the load-data-pointer-PWM command. PWM register filling is described in Section 8.10 Write-PWM-data - write PWM data command bit description[1] Table 28.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 29. Reset state Reset state of configurable bits shown in the command table format for clarity.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator START Power-on VDD and VLCD together Toggle RESET pin (1) Wait minimum 1 ms Send OTP-refresh Set: - mode settings: BPS and INV - LCD/GPO output mode - multiplex driver mode - bias mode - LCD frame frequency If using GPO outputs, set - GPO data - PWM data - PWM frame frequency Send display content Enable the display STOP 013aaa452 (1) Alternatively, it is possible to send the initialize command. Fig 9.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator START Power-on VDD and VLCD together Toggle RESET pin If using GPO outputs, set - GPO data - PWM data - PWM frame frequency (1) Wait minimum 1 ms External clock can be applied now Send OTP-refresh Set: - Mode settings: BPS and INV - Select external clock - GPO output mode - Multiplex driver mode - Bias mode - LCD frame frequency Send display content External clock must be applied by now Enable the display
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.3 Possible display configurations The PCF8536 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 11). It can drive multiplexed LCD with 4, 6, or 8 backplanes and up to 44 segments. The display configurations possible with the PCF8536 depend on the number of active backplane outputs required.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator VDD R= tr 2Cb SDA HOST PROCESSOR/ MICROCONTROLLER 40 to 44 segment drives VDD SCL PCF8536AT 4 to 8 backplanes A0 VSS LCD PANEL (up to 320 elements) 013aaa450 VSS Fig 12. Typical system configuration for the I2C-bus VDD SDI HOST PROCESSOR/ MICROCONTROLLER SCL 40 to 44 segment drives VDD PCF8536BT CE 4 to 8 backplanes LCD PANEL (up to 320 elements) VSS 013aaa451 VSS Fig 13.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. Table 31. Preferred LCD drive modes: summary of characteristics LCD bias configuration V off RMS ----------------------V LCD V on RMS ---------------------V LCD V on RMS [1] VLCD[2] D = ---------------------V off RMS 3 1⁄ 2 0.433 0.661 1.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator V on RMS D = ---------------------- = V off RMS 2 a + 2a + n --------------------------2 a – 2a + n (6) It should be noted that VLCD is sometimes referred to as the LCD operating voltage. 8.4.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.5 LCD drive mode waveforms 8.5.1 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 15. This drawing is also showing the case of line inversion (see Section 8.1.4.2).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.5.2 1:6 Multiplex drive mode When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The PCF8536 allows use of 1⁄3 bias or 1⁄4 bias in this mode as shown in Figure 16 and Figure 17. These waveforms are drawn for the case of line inversion (see Section 8.1.4.2).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Tfr LCD segments VLCD 3VLCD / 4 state 1 state 2 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 VLCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS (a) Waveforms at driver VLCD 3VLCD / 4 state 1 VLCD / 4 VSS -VLCD / 4 -3VLCD / 4 -VLCD VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS state 2 -VLCD
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.5.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator VLCD 3/4 VLCD Tfr frame n Tfr frame n+1 LCD segments state 1 BP0 state 2 1/4 VLCD VSS VLCD 3/4 VLCD BP1 1/4 VLCD VSS VLCD 3/4 VLCD BP2 1/4 VLCD VSS VLCD 3/4 VLCD BP3 1/4 VLCD VSS VLCD 3/4 VLCD BP4 1/4 VLCD VSS VLCD 3/4 VLCD BP5 1/4 VLCD VSS VLCD 3/4 VLCD BP6 1/4 VLCD VSS VLCD 3/4 VLCD BP7 1/4 VLCD VSS VLCD Sn 1/2 VLCD VSS VLCD Sn + 1 1/2 VLCD VSS (a) Waveforms at driver state 1 VLCD 3/4 VLCD 1/2 VLCD 1
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.6 Display register The display register holds the display data while the corresponding multiplex signals are generated. 8.7 Backplane outputs The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane output signals are generated based on the selected LCD multiplex drive mode. • In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.9 Display RAM The display RAM stores the LCD data. Depending on the multiplex drive mode, the arrangement of the RAM is changed.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator • the RAM columns and the segment outputs, • the RAM rows and the backplane outputs. The display RAM bit map, Figure 20, shows row 0 to row 7 which correspond with the backplane outputs BP0 to BP7, and column 0 to column 43 which correspond with the segment outputs S0 to S43.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.9.2 RAM filling in 1:4 multiplex drive mode In the 1:4 multiplex drive mode the RAM is organized in four rows and 44 columns. The eight transmitted data bits are placed in two successive display RAM columns of four rows (see Figure 21). In order to fill the whole four RAM rows, 22 bytes need to be sent to the PCF8536. After the last byte sent, the data pointer must be reset before the next RAM content update.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.9.3 RAM filling in 1:6 multiplex drive mode In the 1:6 multiplex drive mode the RAM is organized in six rows and 42 columns. The eight transmitted data bits are placed in such a way, that a column is filled up (see Figure 23).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Columns Display RAM addresses (columns)/segment outputs (S) 0 1 2 3 4 5 6 7 37 38 39 40 41 0 1 b7 b6 2 b5 3 b4 4 b3 5 b2 Rows Display RAM bits (rows)/backplane outputs (BP) Discarded b7 b6 b5 b4 b3 b2 b1 b0 MSB 0 1 2 3 4 5 6 7 LSB Transmitted data byte 37 38 39 40 41 0 1 2 b7 3 b6 4 b5 5 b4 Discarded b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB Transmitted data byte 0 1 2 3 4 5 6
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.9.4 RAM filling in 1:8 multiplex drive mode In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The eight transmitted data bits are placed into eight rows of one display RAM column (see Figure 25). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8536. After the last byte sent, the data pointer must be reset before the next RAM content update.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Columns Display RAM columns/segment outputs (S) 0 1 2 3 4 5 6 7 35 36 37 38 39 0 b7 1 b6 Rows 2 b5 Display RAM rows/ backplane outputs (BP) 3 b4 4 b3 5 b2 6 b1 7 b0 b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB Transmitted data byte 013aaa460 Fig 26. PWM register filling 8.11 GPO output The PCF8536 contains six independently configured GPO pins (GP0 to GP5).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator PWMI 230 kHz PWM generator channel 0 0 1 PWM value 0 GP0 segment 0 LCD data 1 1 0 0 0 1 1 0 S0/GP0 GP0M[1:0] 230 kHz PWM generator channel 1 0 1 PWM value 1 GP1 segment 1 LCD data 1 1 0 0 0 1 1 0 S1/GP1 GP1M[1:0] 230 kHz PWM generator channel 2 0 1 PWM value 2 GP2 segment 2 LCD data 1 1 0 0 0 1 1 0 S2/GP2 GP2M[1:0] 230 kHz PWM generator channel 3 0 1 PWM value 3 GP3 segment 3 LCD dat
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator fPWM PWM register 0 = 0 0.00 % PWM register 1 = 1 0.78 % PWM register 2 = 32 24.96 % PWM register 3 = 64 49.92 % PWM register 4 = 96 74.88 % PWM register 5 = 127 99.20 % 1 t= 128 x fPWM 001aan569 Fig 28. PWM example waveforms for PWMI = 0 8.11.1 RGB color driving There are six PWM channels that can be arranged as two RGB channels.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator LED supply voltage G R B R G cluster 0 B cluster 1 S0/GP0 S1/GP1 S2/GP2 S3/GP3 S4/GP4 S5/GP5 001aan568 There are six independently configured GPO outputs. Fig 29. Configuration for two RGB clusters Table 35 gives some examples of programming values for the PWM channels in order to achieve the given colors.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 8.11.2 PWM inversion mode The PWM inversion mode can be enabled by setting the PWMI bit to logic 1 (see Table 7 on page 8). The PWMI mode will invert the PWM waveform. By default, all PWM outputs will switch HIGH at the same time. If the PWM output is used to drive external LEDs then this could cause a voltage dip on the power supply of the LEDs.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9. Bus interfaces 9.1 Control byte and register selection After initiating the communication over the bus and sending the slave address (I2C-bus, see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The purpose of this byte is to indicate both, the content for the following data bytes (RAM, command, or PWM data) and to indicate that more control bytes will follow.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 32). SDA SCL data line stable; data valid change of data allowed mba607 Fig 32. Bit transfer 9.2.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle. • A slave receiver which is addressed must generate an acknowledge after the reception of each byte.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9.2.7 I2C-bus slave address Device selection depends on the I2C-bus slave address. Two different I2C-bus slave addresses can be used to address the PCF8536 (see Table 37). Table 37. I2C slave address Slave address Bit 7 6 5 4 3 2 1 MSB 0 0 LSB 1 1 1 0 0 A0 R/W The least significant bit of the slave address byte is bit R/W.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9.2.8.1 Status read out Status read out for I2C-bus operation only. This command will initiate the read out of a fixed value plus the slave address bit A0 from the PCF8536. This read out function will allow the I2C master to confirm the existence of the device on the I2C-bus. Table 38.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 9.3 SPI-bus interface Data transfer to the device is made via a 3 line SPI-bus (see Table 40). There is no output data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive. Table 40.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator R/W = 0 subaddress 0 0 1 control byte R R C S S O1 0 RAM/command byte M L S S B B EXAMPLES a) transmit two bytes of display RAM data 0 0 1 0 0 1 RAM DATA RAM DATA b) transmit two command bytes 0 0 1 1 0 0 COMMAND 0 0 0 COMMAND c) transmit one command byte and two display RAM date bytes 0 0 1 1 0 0 COMMAND 0 0 1 RAM DATA RAM DATA 013aaa465 Data transfers are terminated by de-asserting CE (set CE t
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 10. Internal circuitry VDD A0, RESET, OSCCLK VSS VLCD, VDD, SCL, SDA VLCD VSS BP0 to BP7, S0/GP0 to S5/GP5 S6 to S39 VSS 013aaa472 Fig 41. Device protection diagram for PCF8536AT VDD CE, RESET, OSCCLK SDI, SCL VLCD,VDD VSS VLCD VSS BP0 to BP7, S0/GP0 to S5/GP5 S6 to S39 VSS 013aaa473 Fig 42.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 11. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 42. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 12. Static characteristics Table 43. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1.8 2.5 - 5.5 V - 9.0 [1] V - 0.5 2 A external 9.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 43. Static characteristics …continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit IOL LOW-level output current output sink current; VOL = 0.4 V VDD = 1.8 V 3 4 - mA VDD 3.3 V 5 10 - mA VDD = 1.8 V; VLCD = 2.5 V 0.7 1.1 - mA VDD = 3.3 V; VLCD 5.5 V 1.5 2.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Table 43. Static characteristics …continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit LCD outputs VO output voltage variation on pins BP0 to BP7 [7] - 2.5 +10 mV on pins S0 to S43 [8] - 2.5 +10 mV VLCD = 7 V; on pins BP0 to BP7 [9] - 0.9 5.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 013aaa505 15 IDD(LCD) (µA) VLCD = 9.0 V 10 VLCD = 5.5 V 5 0 -45 -10 25 60 95 Tamb (ºC) Power-down mode is enabled; I2C-bus or SPI-bus inactive. Typical is defined at 25 C. Fig 44. Typical IDD(LCD) in power-down mode with respect to temperature 013aaa507 120 IDD(LCD) (µA) VLCD = 9.0 V 80 40 0 -45 VLCD = 5.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 13. Dynamic characteristics Table 44. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions [1] Min Typ Max Unit 7800 9600 11040 Hz fclk clock frequency output on pin OSCCLK; VDD = 3.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator tRESET(L) RESET 0.3VDD 013aaa475 Fig 48. RESET timing Table 45. Timing characteristics: I2C-bus VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = 40 C to +85 C; unless otherwise specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Timing waveforms see Figure 49.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator protocol bit 7 MSB (A7) START condition (S) tSU;STA tLOW bit 6 (A6) tHIGH 1/f bit 0 (R/W) acknowledge (A) STOP condition (P) SCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tVD;ACK tVD;DAT tHD;DAT tSU;STO 013aaa417 Fig 49. I2C-bus timing waveforms Table 46. Timing characteristics: SPI-bus VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator CE tsu(CE_N) tSCL tclk(H) tr tf trec(CE_N) th(CE_N) 70% SCL 30% tclk(L) tsu th SDI b7 b6 b0 013aaa476 Fig 50. SPI-bus timing PCF8536 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 21 February 2012 © NXP B.V. 2012. All rights reserved.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 14. Package outline TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 E D A X c HE y v M A Z 56 29 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 28 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 52. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Footprint information for reflow soldering of TSSOP56 package SOT364-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 0.500 0.560 8.900 6.100 1.400 0.280 D2 Gx 0.400 14.270 Gy Hx Hy 7.000 16.600 9.150 sot364-1_fr Fig 53.
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PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 19. Abbreviations Table 50.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 20.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 22. Legal information 22.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 24. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.1.4.1 8.1.4.2 8.1.4.3 8.1.4.4 8.1.5 8.1.5.1 8.1.5.2 8.1.6 8.1.7 8.1.8 8.1.9 8.1.10 8.1.11 8.1.12 8.1.13 8.1.14 8.1.15 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.4.1 8.5 8.5.1 8.5.2 8.5.3 8.6 8.7 8.8 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . .
PCF8536 NXP Semiconductors Universal LCD low multiplex driver with 6 channel PWM generator 23 24 Contact information. . . . . . . . . . . . . . . . . . . . . 72 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.