PCF8562 Universal LCD driver for low multiplex rates Rev. 6 — 16 June 2011 Product data sheet 1. General description The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package Name PCF8562TT/2[1] Description Version TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm PCF8562TT/S400/2[2] TSSOP48 plastic thin shrink small outline package; 48 leads; SOT362-1 body width 6.1 mm [1] Not to be used for new designs. Replacement part is PCF85162T/1 for industrial applications.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 5.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 6.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 6.2 Pin description Table 3.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7. Functional description The PCF8562 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Fig 3.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ tr 2Cb VDD VLCD 14 21 32 segment drives SDA 10 HOST MICROPROCESSOR/ MICROCONTROLLER SCL OSC LCD PANEL PCF8562 11 4 backplanes 15 16 17 A0 A1 18 A2 19 (up to 128 elements) 20 SA0 VSS 001aac264 VSS The resistance of the power lines must be kept to a minimum. Fig 4. Typical system configuration The host microcontroller maintains the 2-line I2C-bus communication channel with the PCF8562.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. Table 5.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 2 bias is 1⁄ 2 21 bias is ---------- = 1.528 . 3 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 V off RMS = 2.449V off RMS 4 3 - = 2.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Fig 5. PCF8562 Product data sheet Electro-optical characteristic: relative transmission curve of the liquid All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 June 2011 © NXP B.V. 2011. All rights reserved.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 6. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8562 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 7 and Figure 8. Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr BP0 BP1 Sn Sn+1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. 013aaa209 Vstate1(t) = VSn(t) VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) VBP1(t).
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 9. Tfr BP0 BP1 BP2 Sn Sn+1 Sn+2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 10.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk).
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.10 Display RAM The display RAM is a static 32 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx LCD segments Sn+2 Sn+3 static display RAM filling order b f Sn+1 BP0 rows display RAM 0 rows/backpla
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 12: • In static drive mode the eight transmitted data bits are placed in row 0 as one byte. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit RAM words. • In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.10.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as well). Table 6. Standard RAM filling in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the content of row 2 to be selected for display instead of the content of row 0. In the 1:2 multiplex mode, the content of rows 2 and 3 may be selected instead of rows 0 and 1.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 7.12 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. The commands available to the PCF8562 are defined in Table 9. Table 9.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 11.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 14.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 8. Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL mga807 Fig 15. System configuration 8.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 8.5 I2C-bus controller The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. 8.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. An acknowledgement, after each byte, is asserted only by the PCF8562s that are addressed via address lines A0, A1 and A2.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 9. Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1, A2 VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S31 VSS VSS 001aac269 Fig 19. Device protection circuits PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6 — 16 June 2011 © NXP B.V. 2011. All rights reserved.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 17. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 1.8 - 5.5 V VLCD LCD supply voltage [1] 2.5 - 6.5 V supply current fclk(ext) = 1536 Hz [2] - 8 20 A fclk(ext) = 1536 Hz [2] - 24 60 A 1.0 1.3 1.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 18. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 1/fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S31 (VDD = 5 V) 0.5 V tPD(drv) 013aaa493 Fig 20. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 21. I2C-bus timing waveforms PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Multiple chip operation For large display configurations or for more segments (> 128 elements) to drive please refer to the PCF8576D device. The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 E D A X c HE y v M A Z 48 25 Q A2 (A 3) A1 pin 1 index A θ Lp L 1 detail X 24 w M bp e 2.5 0 5 mm scale DIMENSIONS (mm are the original dimensions). UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z θ mm 1.2 0.15 0.05 1.05 0.85 0.25 0.28 0.17 0.2 0.1 12.6 12.4 6.2 6.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 17.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 18. Abbreviations Table 22.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 19.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 20. Revision history Table 23. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8562 v.6 20110616 Product data sheet - PCF8562_5 Modifications: • • Added design-in and replacement part information Added Section 7.10.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 21.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 22.
PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.3.1 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.11 7.12 7.13 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 9 10 11 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . .