Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsPMICsPMIC - display driver LCD 7 segments + DP, 14 segments, 24 segments 6 characters, 12-d

1. General description

The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display

(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed

LCD containing up to four backplanes and up to 24 segments and can easily be cascaded

for larger LCD applications. The PCF8566 is compatible with most microprocessors or

microcontrollers and communicates via a two-line bidirectional I

C-bus. Communication

overheads are minimized by a display RAM with auto-incremented addressing, by

hardware subaddressing and by display memory switching (static and duplex drive

modes).

2. Features

n Single-chip LCD controller/driver

n 24 segment drives:

u Up to twelve 7-segment numeric characters including decimal pointer

u Up to six 14-segment alphanumeric characters

u Any graphics of up to 96 elements

n Versatile blinking modes

n No external components required (even in multiple device applications)

n Selectable backplane drive conﬁguration: static or 2, 3, 4 backplane multiplexing

n Selectable display bias conﬁguration: static,

⁄

n Internal LCD bias generation with voltage-follower buffers

n 24 × 4-bit RAM for display data storage

n Auto-incremented display data loading across device subaddress boundaries

n Display memory bank switching in static and duplex drive modes

n LCD and logic supplies may be separated

n 2.5 V to 6 V power supply range

n Low power consumption

n Power-saving mode for extremely low power consumption in battery-operated and

telephone applications

n I

C-bus interface

n TTL and CMOS compatible

n Compatible with any 4, 8 or 16-bit microprocessor or microcontroller

n May be cascaded for large LCD applications (up to 1536 segments possible)

n Cascadable with 40-segment LCD driver PCF8576C

n Optimized pinning for plane wiring in both and multiple PCF8566 applications

n Space-saving 40-lead plastic very small outline package (VSO40; SOT158-1)

n Manufactured in silicon gate CMOS process

PCF8566

Universal LCD driver for low multiplex rates

Rev. 07 — 25 February 2009 Product data sheet

Summary of content (48 pages)

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PCF8566 Universal LCD driver for low multiplex rates Rev. 07 — 25 February 2009 Product data sheet 1. General description The PCF8566 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 24 segments and can easily be cascaded for larger LCD applications.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Type number Package Name Description Version PCF8566P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1 PCF8566T VSO40 plastic very small outline package; 40 leads SOT158-1 PCF8566TS[1] VSO40 plastic very small outline package; 40 leads SOT158-1 PCF8566U[2] PCF8566U wire bond die; 40 bonding pads; 2.5 × 2.91 × 0.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 5.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning SDA 1 40 S23 SCL 2 39 S22 SYNC 3 38 S21 CLK 4 37 S20 VDD 5 36 S19 OSC 6 35 S18 A0 7 34 S17 A1 8 33 S16 A2 9 32 S15 SA0 10 VSS 11 PCF8566 31 S14 30 S13 VLCD 12 29 S12 BP0 13 28 S11 BP2 14 27 S10 BP1 15 26 S9 BP3 16 25 S8 S0 17 24 S7 S1 18 23 S6 S2 19 22 S5 S3 20 21 S4 001aai338 Fig 2.
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PCF8566 NXP Semiconductors S8 S7 S6 S5 S4 S3 S2 S1 S0 BP3 Universal LCD driver for low multiplex rates 25 24 23 22 21 20 19 18 17 16 15 BP1 S9 26 14 BP2 S10 27 13 BP0 S11 28 12 VLCD S12 29 S13 30 11 VSS S14 31 10 SA0 S15 32 9 A2 S16 33 8 A1 S17 34 7 A0 S18 35 6 OSC 36 37 38 39 40 1 2 3 4 5 S19 S20 S21 S22 S23 SDA SCL SYNC CLK VDD PCF8566U mbh783 Fig 3. Pin configuration for PCF8566U 6.2 Pin description Table 3.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 3. Pin description …continued Symbol Pin Description BP0 13 LCD backplane outputs BP2 14 BP1 15 BP3 16 S0 to S23 17 to 40 [1] LCD segment outputs The substrate (rear side of the die) is wired to VDD but should not be electrically connected. 7. Functional description The PCF8566 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ trise 2 Cbus HOST MICROPROCESSOR/ MICROCONTROLLER VDD SDA SCL OSC VLCD 5 12 1 17 to 40 24 segment drives PCF8566 2 6 13 to 16 7 A0 8 A1 9 A2 10 4 backplanes LCD PANEL (up to 96 elements) 11 SA0 VSS mgg385 VSS Fig 4. Typical system configuration 7.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 5. Preferred LCD drive modes: summary of characteristics LCD drive mode Number of: Backplanes Bias levels LCD bias configuration static 1 2 static 0 1 ∞ 1:2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 4 1⁄ 3 0.333 0.745 2.236 4 1⁄ 3 0.333 0.638 1.915 4 1⁄ 3 0.333 0.577 1.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 21 3 • 1:4 multiplex with 1⁄2 bias is ---------- = 1.528 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS ) 4 × 3) • 1:4 multiplex (1⁄2 bias): V LCD = (--------------------- = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 5. Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF8566 allows the use of 1⁄2 bias or 1⁄3 bias (see Figure 6 and Figure 7). Tfr VLCD BP0 LCD segments VLCD / 2 VSS state 1 VLCD BP1 state 2 VLCD / 2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD BP1 state 2 2VLCD / 3 VLCD / 3 VSS VLCD Sn Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl747 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as shown in Figure 8. Tfr VLCD BP0 BP1 LCD segments 2VLCD / 3 VLCD / 3 VSS state 1 VLCD 2VLCD / 3 state 2 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD Sn Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.4.4 1:4 multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 9.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate for data reception from the I2C-bus.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates The lower clock frequency has the disadvantage of increasing the response time when large amounts of display data are transmitted on the I2C-bus. When a device is unable to process a display data byte before the next one arrives, it holds the SCL line LOW until the first display data byte is stored. This slows down the transmission rate of the I2C-bus but no data loss occurs. 7.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates display RAM addresses (columns)/segment outputs (S) 0 1 2 3 4 19 20 21 22 23 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 mgg389 Fig 10.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 7.13 Sub-address counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter match with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the device select command (see Table 14 and Table 21).
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 7. Blink frequencies Blinking mode Normal operating mode ratio Power saving mode ratio Blink frequency off - - blinking off 1 f clk f blink = --------------92160 f elk f blink = --------------15360 2 Hz 2 f clk f blink = ------------------184320 f clk f blink = --------------30720 1 Hz 3 f clk f blink = ------------------368640 f clk f blink = --------------61440 0.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 8.1.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are illustrated in Figure 13.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates • A master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the master receiver must leave the data line HIGH during the 9th pulse to not acknowledge. The master will now generate a STOP condition.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates R/W slave address S 0 1 1 1 1 1 A 0 0 1 byte 001aai455 Fig 16. Slave address structure Two displays controlled by PCF8566 can be recognized on the same I2C-bus which allows: • Up to 16 PCF8566s on the same I2C-bus for very large LCD applications (see Section 13) • The use of two types of LCD multiplex on the same I2C-bus The I2C-bus protocol is shown in Figure 17.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 8.3 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 10. LCD bias configuration command bit description LCD bias Bit B 1⁄ 3 bias 0 1⁄ 2 bias 1 Table 11. Display status command bit description[1] Display status Bit E disabled (blank) 0 enabled 1 [1] The possibility to disable the display allows implementation of blinking under external control. Table 12.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 8.3.5 Blink command Table 16. Blink frequency command bit description Blink frequency Bit BF1 BF0 off 0 0 1 0 1 2 1 0 3 1 1 Table 17. Blink mode command bit description Blink mode Bit A Normal blinking 0 Alternate RAM bank blinking 1 8.4 Display controller The display controller executes the commands identified by the command decoder.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 10. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 11. Static characteristics Table 19. Static characteristics VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.5 - 6.0 V VLCD LCD supply voltage VDD − 6.0 - VDD − 2.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 19. Static characteristics …continued VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 11.2 Typical LCD output characteristics mgg399 6 RBP (kΩ) mgg400 12 RS (kΩ) 8 4 −40 °C 4 2 +25 °C +85 °C 0 0 0 2 4 6 VDD (V) 8 VDD = 5 V; Tamb = −40 °C to +85 °C. 0 4 6 VDD (V) 8 VDD = 5 V. Fig 22. Backplane output impedance BP0 to BP3 (RBP) Fig 23. Segment output impedance S0 to S23 (RS) PCF8566_7 Product data sheet 2 © NXP B.V. 2009. All rights reserved. Rev.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 12. Dynamic characteristics Table 20. Dynamic characteristics VSS = 0 V; VDD = 2.5 V to 6.0 V; VLCD = VDD − 2.5 V to VDD − 6.0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. [1] Symbol Parameter Conditions clock frequency normal mode; VDD = 5 V Min Typ Max Unit 125 200 315 kHz 21 31 48 kHz Clock fclk [2] power saving mode; VDD = 3.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 1 fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3 S0 to S23 (VDD = 5 V) 0.5 V tPD(drv) mgg391 Fig 24. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 25. I2C-bus timing waveforms PCF8566_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 13. Application information 13.1 Cascaded operation Large display configurations of up to sixteen PCF8566s can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). Table 21.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates VLCD VDD 5 12 SDA 1 SCL 2 SYNC 17 to 40 24 segment drives LCD PANEL PCF8566 3 CLK 4 OSC 6 7 (up to 1536 elements) 13 to 16 8 A0 9 A1 10 A2 11 SA0 VSS BP0 to BP3 (open-circuit) VLCD VDD R≤ trise 2 Cbus VDD VLCD 5 HOST MICROPROCESSOR/ MICROCONTROLLER SDA SCL SYNC CLK OSC 12 1 17 to 40 2 24 segment drives PCF8566 3 4 13 to 16 6 4 backplanes BP0 to BP3 7 A0 8 A1 9 A2 10 11 mgg384 SA0 VSS VSS Fig 2
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 27. Synchronization of the cascade for the various PCF8566 drive modes PCF8566_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Single plane wiring of packaged PCF8566s is illustrated in Figure 28.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 14. Package outline seating plane DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 ME D A2 L A A1 c e Z w M b1 (e 1) b MH 21 40 pin 1 index E 1 20 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c mm 4.7 0.51 4 1.70 1.14 0.53 0.38 0.36 0.23 52.5 51.5 inches 0.19 0.02 0.16 0.067 0.045 0.021 0.015 0.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates VSO40: plastic very small outline package; 40 leads SOT158-1 D E A X c y HE v M A Z 40 21 Q A2 A (A 3) A1 θ pin 1 index Lp L 1 detail X 20 w M bp e 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 2.7 0.3 0.1 2.45 2.25 0.25 0.42 0.30 0.22 0.14 15.6 15.2 7.6 7.5 0.762 12.3 11.8 2.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 15. Bare die outline Wire bond die; 40 bonding pads; 2.5 x 2.91 x 0.381 mm PCF8566U D e A 24 23 22 21 PC8566-1 25 20 19 18 17 16 C1 15 e 26 14 F 27 13 28 12 29 x 30 0 11 0 31 y E 10 32 9 33 8 C2 34 7 35 6 P4 P3 P2 36 37 38 39 40 1 2 3 4 5 P1 X 0 0.5 detail X 1 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A D E e P1(1) P2(2) P3(1) P4(2) 0.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Bonding pad description All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 31).
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 22. Bonding pad description …continued All x/y coordinates represent the position of the center of each pad with respect to the center (x/y = 0) of the chip (see Figure 31). Symbol Pad X (µm) Y (µm) S21 38 −630 −1235 S22 39 −430 −1235 S23 40 −230 −1235 Description REF REF C1 F REF C2 001aai300 Fig 32. Alignment marks Table 23.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates G A C H D B F E 001aai237 marking code Fig 33. Tray details 001aaj619 Fig 34. Tray alignment Table 24. Tray dimensions Symbol Description Value A pocket pitch; x direction 4.43 mm B pocket pitch; y direction 4.43 mm C pocket width; x direction 3.04 mm D pocket width; y direction 3.04 mm PCF8566_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates Table 24. Tray dimensions …continued Symbol Description Value E tray width; x direction 50.8 mm F tray width; y direction 50.8 mm G cut corner to pocket 1,1 center 5.47 mm H cut corner to pocket 1,1 center 5.47 mm x number of pockets; x direction 10 y number of pockets; y direction 10 18. Soldering of SMD packages This text provides a very brief insight into a complex technology.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates • Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 35. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 19. Abbreviations Table 27.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 20. Revision history Table 28. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8566_7 20090225 Product data sheet - PCF8566_6 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • • • Legal texts have been adapted to the new company name where appropriate.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 21. Legal information 21.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCF8566 NXP Semiconductors Universal LCD driver for low multiplex rates 23. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.5 7.5.1 7.5.2 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 8 8.1 8.1.1 8.1.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . .