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Table Of Contents

1. General description

The PCF8593 is a CMOS

clock and calendar circuit, optimized for low power

consumption. Addresses and data are transferred serially via the two-line bidirectional

C-bus. The built-in word address register is incremented automatically after each written

or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM

are used for the clock, calendar, and counter functions. The next 8 bytes can be

programmed as alarm registers or used as free RAM space.

2. Features and benefits

 I

C-bus interface operating supply voltage: 2.5 V to 6.0 V

 Clock operating supply voltage 1.0 V to 6.0 V at 0 °Cto+70°C

 8 bytes scratchpad RAM (when alarm not used)

 Data retention voltage: 1.0 V to 6.0 V

 External RESET

input resets I

C interface only

 Operating current (at f

SCL

= 0 Hz, 32 kHz time base, V

= 2.0 V): typical 1 μA

 Clock function with four year calendar

 Universal timer with alarm and overflow indication

 24 hour or 12 hour format

 32.768 kHz or 50 Hz time base

 Serial input and output bus (I

C-bus)

 Automatic word address incrementing

 Programmable alarm, timer, and interrupt function

 Space-saving SO8 package available

 Slave addresses: A3h for reading, A2h for writing

3. Ordering information

PCF8593

Low power clock and calendar

Rev. 04 — 6 October 2010 Product data sheet

1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.

Table 1. Ordering information

Type number Package

Name Description Version

PCF8593P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1

PCF8593T SO8 plastic small outline package; 8 leads;

body width 3.9 mm

SOT96-1

Summary of content (35 pages)

PAGE 1
PCF8593 Low power clock and calendar Rev. 04 — 6 October 2010 Product data sheet 1. General description The PCF8593 is a CMOS1 clock and calendar circuit, optimized for low power consumption. Addresses and data are transferred serially via the two-line bidirectional I2C-bus. The built-in word address register is incremented automatically after each written or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM are used for the clock, calendar, and counter functions.
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PCF8593 NXP Semiconductors Low power clock and calendar 4. Marking Table 2. Marking codes Type number Marking code PCF8593P PCF8593P PCF8593T 8583T 5. Block diagram VDD OSCI OSCILLATOR DIVIDER OSCO INT RESET RESET CONTROL LOGIC PCF8593 SCL I2C-BUS INTERFACE ADDRESS REGISTER SDA 00h control/status 01h hundredth second 02h seconds 03h minutes 04h hours 05h year/date 06h weekdays/months 07h timer 08h alarm control to 0Fh alarm or RAM 013aaa379 VSS Fig 1.
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PCF8593 NXP Semiconductors Low power clock and calendar 6. Pinning information 6.1 Pinning OSCI 1 OSCO 2 8 VDD 7 INT PCF8593P RESET 3 6 SCL VSS 4 5 SDA 013aaa380 Top view. For mechanical details, see Figure 24. Fig 2. Pin configuration for DIP8 (PCF8593P) OSCI 1 OSCO 2 8 VDD 7 INT PCF8593T RESET 3 6 SCL VSS 4 5 SDA 013aaa381 Top view. For mechanical details, see Figure 25. Fig 3. Pin configuration for SO8 (PCF8593T) 6.2 Pin description Table 3.
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PCF8593 NXP Semiconductors Low power clock and calendar 7. Functional description The PCF8593 contains sixteen 8 bit registers with an 8 bit auto-incrementing address register, an on-chip 32.768 kHz oscillator circuit, a frequency divider and a serial two-line bidirectional I2C-bus interface. The first 8 registers (memory addresses 00h to 07h) are designed as addressable 8 bit parallel registers. The first register (memory address 00h) is used as a control and status register.
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PCF8593 NXP Semiconductors Low power clock and calendar 7.3 Control and status register The control and status register is defined as the memory location 00h with free access for reading and writing via the I2C-bus. All functions and options are controlled by the contents of the control and status register (see Figure 4).
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PCF8593 NXP Semiconductors Low power clock and calendar 7.4 Counter registers The format for 24 hour or 12 hour clock modes can be selected by setting the most significant bit of the hours counter register. The format of the hours counter is shown in Figure 5.
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PCF8593 NXP Semiconductors Low power clock and calendar In the event-counter mode, events are stored in BCD format. D5 is the most significant and D0 the least significant digit. The divider is by-passed. In the different modes the counter registers are programmed and arranged as shown in Figure 8. Counter cycles are listed in Table 4.
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PCF8593 NXP Semiconductors Low power clock and calendar Table 4.
PAGE 9
PCF8593 NXP Semiconductors Low power clock and calendar MSB 7 LSB 6 5 4 3 2 1 0 memory location 08h timer function: 000 001 010 011 100 101 110 111 no timer hundredths of a second seconds minutes hours days not used test mode, all counters in parallel timer interrupt enable: 0 1 timer flag, no interrupt timer flag, interrupt clock alarm function: 00 01 10 11 no clock alarm daily alarm weekday alarm dated alarm timer alarm enable: 0 1 no timer alarm timer alarm alarm interrupt enable: 013
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PCF8593 NXP Semiconductors Low power clock and calendar MSB 7 LSB 6 5 4 3 2 1 0 memory location 0Eh (alarm_weekday/month) weekday 0 enabled when set weekday 1 enabled when set weekday 2 enabled when set weekday 3 enabled when set weekday 4 enabled when set weekday 5 enabled when set weekday 6 enabled when set not used 013aaa375 Fig 10. Selection of alarm weekdays 7.7 Timer The timer (location 07h) is enabled by setting the control and status register to XX0X X1XX.
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PCF8593 NXP Semiconductors Low power clock and calendar MUX oscillator mode select CLOCK/CALENDAR counter control ALARM clock alarm 7 6 5 4 3 2 TIMER alarm control 1 0 timer alarm overflow 7 6 timer control 5 4 3 2 1 0 ALARM CONTROL REGISTER CONTROL/STATUS REGISTER (1) alarm interrupt timer overflow interrupt INT 013aaa377 (1) If the alarm enable bit of the control and status register is reset (logic 0), a 1 Hz signal is observed on the interrupt pin INT. Fig 11.
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PCF8593 NXP Semiconductors Low power clock and calendar this mode, the timer (location 07h) increments once for every one, one hundred, ten thousand, or 1 million events, depending on the value programmed in bits 0, 1 and 2 of the alarm control register. In all other events, the timer functions are as in the clock mode.
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PCF8593 NXP Semiconductors Low power clock and calendar In the 50 Hz clock mode or event-counter mode the oscillator is disabled and the oscillator input is switched to a high-impedance state. This allows the user to feed the 50 Hz reference frequency or an external high speed event signal into the input OSCI. 7.10.1 Designing When designing the printed-circuit board layout, keep the oscillator components as close to the IC package as possible, and keep all other signal lines as far away as possible.
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PCF8593 NXP Semiconductors Low power clock and calendar 8. Characteristics of the I2C-bus 8.1 Characteristics The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy. 8.1.1 Bit transfer One data bit is transferred during each clock pulse (see Figure 14).
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PCF8593 NXP Semiconductors Low power clock and calendar SDA SCL MASTER TRANSMITTER RECEIVER SLAVE TRANSMITTER RECEIVER SLAVE RECEIVER MASTER TRANSMITTER RECEIVER MASTER TRANSMITTER mba605 Fig 16. System configuration 8.1.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
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PCF8593 NXP Semiconductors Low power clock and calendar 8.2 I2C-bus protocol 8.2.1 Addressing Before any data is transmitted on the I2C-bus, the device which must respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock and calendar acts as a slave receiver or slave transmitter. The clock signal SCL is only an input signal but the data signal SDA is a bidirectional line. The clock and calendar slave address is shown in Table 5.
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PCF8593 NXP Semiconductors Low power clock and calendar acknowledgement from slave S SLAVE ADDRESS 0 A acknowledgement from slave REGISTER ADDRESS A S acknowledgement from slave SLAVE ADDRESS 1 A DATA A n bytes R/W R/W acknowledgement from slave auto increment memory register address (1) no acknowledgement from master 1 DATA P last byte auto increment memory register address 013aaa041 (1) At this moment master transmitter becomes master receiver and PCF8593 slave receiver becomes s
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PCF8593 NXP Semiconductors Low power clock and calendar 9. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Max Unit −0.8 +0.7 V IDD supply current - 50 mA ground supply current - 50 mA VI input voltage −0.8 VDD + 0.
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PCF8593 NXP Semiconductors Low power clock and calendar 10. Characteristics 10.1 Static characteristics Table 7. Static characteristics VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C unless otherwise specified. Min Typ[1] Max Unit I2C-bus active 2.5 - 6.0 V I2C-bus 1.0 - 6.0 V Symbol Parameter Conditions VDD supply voltage operating mode inactive quartz oscillator supply current IDD Tamb = 0 °C to +70 °C [2] 1.0 - 6.0 V Tamb = −40 °C to +85 °C [2] 1.2 - 6.
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PCF8593 NXP Semiconductors Low power clock and calendar 001aam493 8 lDD (μA) 6 4 2 0 0 2 4 6 VDD (V) fSCL = 32 kHz; Tamb = 25 °C Fig 21. Typical supply current in clock mode as a function of supply voltage PCF8593 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 6 October 2010 © NXP B.V. 2010. All rights reserved.
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PCF8593 NXP Semiconductors Low power clock and calendar 10.2 Dynamic characteristics Table 8. Dynamic characteristics VDD = 2.5 V to 6.0 V; VSS = 0 V; Tamb = −40 °C to +85 °C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 20 25 30 pF - 0.2 - ppm - - 1 MHz Oscillator COSCO capacitance on pin OSCO Δfosc/fosc relative oscillator frequency variation fclk(ext) external clock frequency for ΔVDD = 100 mV; Tamb = 25 °C; VDD = 1.
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PCF8593 NXP Semiconductors Low power clock and calendar PROTOCOL START CONDITION (S) tSU;STA BIT 7 MSB (A7) tLOW BIT 6 (A6) tHIGH BIT 0 LSB (R/W) ACKNOWLEDGE (A) STOP CONDITION (P) 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO mbd820 Fig 22. I2C-bus timing diagram; rise and fall times refer to VIL and VIH PCF8593 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 6 October 2010 © NXP B.V. 2010.
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PCF8593 NXP Semiconductors Low power clock and calendar 11. Application information 11.1 Oscillator frequency adjustment 11.1.1 Method 1: Fixed OSCI capacitor By evaluating the average capacitance necessary for the application layout a fixed capacitor can be used. The frequency is best measured via the 1 Hz signal which can be programmed to occur at the interrupt output (pin 7).
PAGE 24
PCF8593 NXP Semiconductors Low power clock and calendar SDA RESET VDD RESET VDD MASTER TRANSMITTER/ RECEIVER 1F SCL VSS VDD RESET SCL CLOCK/CALENDAR OSCI PCF8593 OSCO SDA VSS VDD R SDA SCL (I2C-bus) R R: pull-up resistor tr R= Cb 013aaa389 Fig 23. Application example PCF8593 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 04 — 6 October 2010 © NXP B.V. 2010. All rights reserved.
PAGE 25
PCF8593 NXP Semiconductors Low power clock and calendar 12. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil) SOT97-1 ME seating plane D A2 A A1 L c Z w M b1 e (e 1) b MH b2 5 8 pin 1 index E 1 4 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.14 0.53 0.38 1.07 0.89 0.36 0.23 9.8 9.2 6.48 6.20 2.
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PCF8593 NXP Semiconductors Low power clock and calendar SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 Q A2 A (A 3) A1 pin 1 index θ Lp L 4 1 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.
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PCF8593 NXP Semiconductors Low power clock and calendar 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits.
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PCF8593 NXP Semiconductors Low power clock and calendar 13.
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PCF8593 NXP Semiconductors Low power clock and calendar temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”.
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PCF8593 NXP Semiconductors Low power clock and calendar 14. Abbreviations Table 11.
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PCF8593 NXP Semiconductors Low power clock and calendar 15.
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PCF8593 NXP Semiconductors Low power clock and calendar 16. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8593 v.4 20101006 Product data sheet - PCF8593_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate.
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PCF8593 NXP Semiconductors Low power clock and calendar 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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PCF8593 NXP Semiconductors Low power clock and calendar Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.
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PCF8593 NXP Semiconductors Low power clock and calendar 19. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.10.1 7.11 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.2.1 8.2.2 9 10 10.1 10.2 11 11.1 11.1.1 11.1.2 11.1.3 12 13 13.1 13.2 13.3 13.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . .