Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsFETsPHT4NQ10T,135, MOSFET

PHT4NQ10T

TrenchMOS™ standard level FET

Rev. 02 — 2 May 2002 Product data

M3D087

1. Description

N-channel enhancement mode ﬁeld-effect transistor in a plastic package using

TrenchMOS™ technology.

Product availability:

PHT4NQ10T in SOT223.

2. Features

■ TrenchMOS™ technology

■ Very fast switching

■ Surface mount package.

3. Applications

■ Primary side switch in DC to DC converters

■ High speed line driver

■ Fast general purpose switch.

4. Pinning information

Table 1: Pinning - SOT223, simpliﬁed outline and symbol

Pin Description Simpliﬁed outline Symbol

1 gate (g)

SOT223

2 drain (d)

3 source (g)

4 drain (d)

123

MSB002 - 1

Top view

MBB076

Summary of content (12 pages)

PAGE 1
PHT4NQ10T TrenchMOS™ standard level FET M3D087 Rev. 02 — 2 May 2002 Product data 1. Description N-channel enhancement mode field-effect transistor in a plastic package using TrenchMOS™ technology. Product availability: PHT4NQ10T in SOT223. 2. Features ■ TrenchMOS™ technology ■ Very fast switching ■ Surface mount package. 3. Applications ■ Primary side switch in DC to DC converters ■ High speed line driver ■ Fast general purpose switch. 4.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 5. Quick reference data Table 2: Quick reference data Symbol Parameter Conditions Typ Max Unit VDS drain-source voltage (DC) 25 °C ≤ Tj ≤ 150 °C - 100 V ID drain current (DC) Tsp = 25 °C; VGS = 10 V - 3.5 A Tsp = 25 °C - 6.9 W - 150 °C Tj = 25 °C 200 250 mΩ Tj = 150 °C - 575 mΩ Ptot total power dissipation Tj junction temperature RDSon drain-source on-state resistance VGS = 10 V; ID = 1.75 A 6.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 03aa17 120 03aa25 120 Pder I der (%) (%) 80 80 40 40 0 0 0 50 100 200 150 0 50 150 100 Tsp (°C) 200 Tsp (°C) VGS ≥ 10 V P tot P der = ---------------------- × 100% P ° ID I der = ------------------- × 100% I ° tot ( 25 C ) D ( 25 C ) Fig 1. Normalized total power dissipation as a function of solder point temperature. 03aa88 102 IAS (A) tp = 10 µs 10 03aa97 10 Limit RDSon = VDS/ID ID (A) Fig 2.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 7. Thermal characteristics Table 4: Thermal characteristics Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point mounted on a metal clad substrate; Figure 5 Rth(j-a) thermal resistance from junction to ambient mounted on a printed circuit board; minimum footprint Min Typ Max Unit - 18 K/W 150 - K/W 7.1 Transient thermal impedance 03aa87 102 Zth(j-sp) (K/W) 10 δ = 0.5 0.2 0.1 1 0.05 0.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 8. Characteristics Table 5: Characteristics Tj = 25 °C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Static characteristics V(BR)DSS VGS(th) drain-source breakdown voltage ID = 250 µA; VGS = 0 V Tj = 25 °C 100 130 - V Tj = −55 °C 89 - - V 2 3 4 V Tj = 150 °C; Figure 10 1.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 03aa90 10 03aa92 10 Tj = 25 °C ID ID VGS = 10 V (A) VDS > ID X RDSon (A) 8 8 6V 6 6 5.5 V Tj = 25 °C 4 4 150 °C 5V 4.8 V 2 2 4.6 V 4.2 V 0 0 0.4 0.8 0 2 1.6 1.2 0 2 4 6 8 VGS (V) VDS (V) Tj = 25 °C Tj = 25 °C and 150 °C; VDS > ID × RDSon Fig 6. Output characteristics: drain current as a function of drain-source voltage; typical values. Fig 7.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 03aa32 03aa35 10-1 5 ID (A) VGS(th) (V) 4 max 10-2 3 typ 10-3 2 min 10-4 1 10-5 0 10-6 -60 0 60 120 o Tj ( C) 180 0 2 typ max 4 6 VGS (V) Tj = 25 °C; VDS = 5 V ID = 1 mA; VDS = VGS Fig 10. Gate-source threshold voltage as a function of junction temperature. 03aa93 VDS > ID X RDSon Tj = 25 °C (S) Fig 11. Sub-threshold drain current as a function of gate-source voltage.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 03aa94 10 03aa96 15 IS (A) VDS = 20 V ID = 3.5 A VGS (V) Tj = 25 °C 8 10 6 VDS = 80 V Tj = 150 °C 4 5 25 °C 2 0 0 0 0.2 0.4 0.6 0.8 1 1.2 0 4 VSD (V) Tj = 25 °C and 150 °C; VGS = 0 V QG (nC) 12 ID = 3.5 A; VDS = 80 V Fig 14. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values. Fig 15. Gate-source voltage as a function of gate charge; typical values.
PAGE 9
PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 9. Package outline Plastic surface mounted package; collector pad for good heat transfer; 4 leads D SOT223 E B A X c y HE v M A b1 4 Q A A1 1 2 3 Lp bp e1 w M B detail X e 0 2 4 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y mm 1.8 1.5 0.10 0.01 0.80 0.60 3.1 2.9 0.32 0.22 6.7 6.3 3.7 3.3 4.6 2.3 7.3 6.7 1.1 0.7 0.95 0.85 0.2 0.1 0.
PAGE 10
PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 10. Revision history Table 6: Revision history Rev Date 02 20020502 CPCN Description - Product data (9397 750 09581) Modifications: • 01 20000731 - Additional IDSS data added. Product specification; initial version. © Koninklijke Philips Electronics N.V. 2002. All rights reserved. 9397 750 09581 Product data Rev.
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PHT4NQ10T Philips Semiconductors TrenchMOS™ standard level FET 11. Data sheet status Data sheet status[1] Product status[2] Definition Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date.
PAGE 12
Philips Semiconductors PHT4NQ10T TrenchMOS™ standard level FET Contents 1 2 3 4 5 6 7 7.1 8 9 10 11 12 13 14 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pinning information . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Limiting values. . . . . . . . . . . . . . . . . . .