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PMC85XP

30 V P-channel MOSFET with pre-biased NPN transistor

15 May 2013 Product data sheet

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1. General description

P-channel enhancement mode Field-Effect Transistor (FET) in Trench MOSFET

technology and NPN Resistor-Equipped Transistor (RET) together in a leadless medium

power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package.

2. Features and benefits

•

Trench MOSFET technology

•

NPN transistor built-in bias resistors

•

Small and leadless ultra thin SMD plastic package: 2 x 2 x 0.65 mm

•

Exposed drain pad for excellent thermal conduction

3. Applications

•

Charging switch for portable devices

•

High-side load switch

•

USB port overvoltage protection

•

Power management in battery-driven portables

•

Hard disk and computing power management

4. Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

P-channel Trench MOSFET

drain-source voltage - - -30 V

gate-source voltage

= 25 °C

-12 - 12 V

drain current V

= -4.5 V; T

amb

= 25 °C; t ≤ 5 s [1] - - -3.4 A

P-channel Trench MOSFET; static characteristics

DSon

drain-source on-state

resistance

= -4.5 V; I

= -2.6 A; T

= 25 °C - 85 110 mΩ

NPN RET

CEO

collector-emitter

voltage

amb

= 25 °C; open base - - 50 V

output current - - 100 mA

Summary of content (15 pages)

PAGE 1
DF N2 020 -6 PMC85XP 30 V P-channel MOSFET with pre-biased NPN transistor 15 May 2013 Product data sheet 1. General description P-channel enhancement mode Field-Effect Transistor (FET) in Trench MOSFET technology and NPN Resistor-Equipped Transistor (RET) together in a leadless medium power DFN2020-6 (SOT1118) Surface-Mounted Device (SMD) plastic package. 2.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor Symbol Parameter Conditions Min Typ Max Unit NPN RET R1 bias resistor 1 3.3 4.7 6.1 kΩ R2 bias resistor 2 - 47 - kΩ [1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and mounting pad 2 for drain 6 cm 5. Pinning information Table 2.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit Tj = 25 °C - -30 V -12 12 V P-channel Trench MOSFET VDS drain-source voltage VGS gate-source voltage ID drain current VGS = -4.5 V; Tamb = 25 °C; t ≤ 5 s [1] - -3.4 A VGS = -4.5 V; Tamb = 25 °C [1] - -2.6 A VGS = -4.5 V; Tamb = 100 °C [1] - -1.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 017aaa123 120 Pder (%) Ider (%) 80 80 40 40 0 - 75 Fig. 1. 017aaa124 120 - 25 25 75 125 Tj (°C) 0 - 75 175 Normalized total power dissipation as a function of junction temperature Fig. 2.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor Symbol Parameter Conditions Rth(j-sp) thermal resistance from junction to solder point Min Typ Max Unit - 10 15 K/W [1] - 233 270 K/W [2] - 110 127 K/W - 25 30 K/W NPN RET Rth(j-a) thermal resistance from junction to ambient Rth(j-sp) in free air thermal resistance from junction to solder point [1] [2] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper; tin-plated and stan
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 017aaa399 103 Zth(j-a) (K/W) 102 duty cycle = 1 0.75 0.5 0.33 0.25 0.2 10 0.1 0.05 0.02 1 0.01 0 10-1 10-5 10-4 10-3 10-2 FR4 PCB, mounting pad for drain 6 cm Fig. 5. 10-1 1 102 10 tp (s) 103 2 P-channel Trench MOSFET: Transient thermal impedance from junction to ambient as a function of pulse duration; typical values 10. Characteristics Table 7.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor Symbol Parameter Crss reverse transfer capacitance td(on) turn-on delay time tr rise time td(off) tf Conditions Min Typ Max Unit - 40 - pF VDS = -15 V; ID = -2.6 A; RG(ext) = 6 Ω; - 3 - ns VGS = -4.5 V; Tj = 25 °C - 15 - ns turn-off delay time - 112 - ns fall time - 48 - ns P-channel Trench MOSFET; source-drain diode VSD source-drain voltage IS = -1.2 A; VGS = 0 V; Tj = 25 °C - -0.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor -5 ID (A) aaa-003662 -4.5 V -1.8 V -4 017aaa401 -10-3 -2.5 V VGS = -1.7 V ID (A) -3 -10-4 -2 (1) (2) (3) -1.5 V -1 -1.2 V 0 Fig. 6. 0 -0,5 -1.0 -1.5 VDS (V) -10-5 -2.0 0 -0.25 -0.50 Tj = 25 °C Tj = 25 °C; VDS = −5 V Output characteristics: drain current as a function of drain-source voltage; typical values (1) minimum values (2) typical values (3) maximum values Fig. 7. aaa-003663 300 VGS = -1.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 017aaa404 -3 017aaa405 2.0 a ID (A) 1.5 -2 1.0 -1 (2) (1) 0.5 0 0 -0.5 -1.0 -1.5 0 -60 -2.0 -2.5 VGS (V) VDS > ID × RDSon 0 60 120 Tj (°C) 180 Fig. 11. Normalized drain-source on-state resistance as a function of junction temperature; typical values (1) Tj = 25 °C (2) Tj = 150 °C Fig. 10. Transfer characteristics: drain current as a function of gate-source voltage; typical values 017aaa406 -1.
PAGE 10
PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 017aaa408 -6 VDS VGS (V) ID -4 VGS(pl) VGS(th) VGS -2 QGS1 QGS2 QGS QGD QG(tot) 017aaa137 0 0 2 4 QG (nC) Fig. 15. Gate charge waveform definitions 6 ID = −3.3 A; VDS = −10 V; Tamb = 25 °C Fig. 14. Gate-source voltage as a function of gate charge; typical values 017aaa409 -3.2 IS (A) -2.4 -1.6 (1) (2) -0.8 0 0 -0.4 -0.8 VSD (V) -1.2 VGS = 0 V (1) Tamb = 150 °C (2) Tamb = 25 °C Fig. 16.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 11. Test information P t2 duty cycle δ = t1 t2 t1 t 006aaa812 Fig. 17. Duty cycle definition 12. Package outline 2.1 1.9 0.65 max 1.1 0.9 2.1 1.9 0.77 0.57 (2×) 0.54 0.44 (2×) 0.04 max 3 4 1 6 0.65 (4×) 0.35 0.25 (6×) 0.3 0.2 Dimensions in mm 10-05-31 Fig. 18. Package outline DFN2020-6 (SOT1118) PMC85XP Product data sheet All information provided in this document is subject to legal disclaimers.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 13. Soldering 2.1 0.65 0.49 0.65 0.49 0.3 0.4 (6×) (6×) solder lands 0.875 solder paste 1.05 1.15 (2×) (2×) 2.25 solder resist 0.875 occupied area Dimensions in mm 0.35 (6×) 0.72 (2×) 0.45 (6×) 0.82 (2×) sot1118_fr Fig. 19. Reflow soldering footprint for DFN2020-6 (SOT1118) 14. Revision history Table 8. Revision history Data sheet ID Release date Data sheet status Change notice Supersedes PMC85XP v.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 15.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
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PMC85XP NXP Semiconductors 30 V P-channel MOSFET with pre-biased NPN transistor 16. Contents 1 General description ............................................... 1 2 Features and benefits ............................................1 3 Applications ........................................................... 1 4 Quick reference data ............................................. 1 5 Pinning information ............................................... 2 6 Ordering information ....................