Datasheet

PSMN015-100B_6 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 06 — 17 December 2009 2 of 12
NXP Semiconductors
PSMN015-100B
N-channel TrenchMOS SiliconMAX standard level FET
2. Pinning information
[1] It is not possible to make a connection to pin 2.
3. Ordering information
4. Limiting values
Table 2. Pinning information
Pin Symbol Description Simplified outline Graphic symbol
1G gate
SOT404 (D2PAK)
2D drain
[1]
3S source
mb D mounting base; connected to
drain
mb
13
2
S
D
G
m
bb076
Table 3. Ordering information
Type number Package
Name Description Version
PSMN015-100B D2PAK plastic single-ended surface-mounted package (D2PAK); 3 leads (one
lead cropped)
SOT404
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage T
j
≥ 25 °C; T
j
≤ 175 °C - 100 V
V
DGR
drain-gate voltage T
j
≤ 175 °C; T
j
≥ 25 °C; R
GS
=20kΩ -100V
V
GS
gate-source voltage -20 20 V
I
D
drain current V
GS
=10V; T
mb
= 100 °C; see Figure 1 -60.8A
V
GS
=10V; T
mb
=25°C; see Figure 1 and 3 -75A
I
DM
peak drain current t
p
≤ 10 µs; pulsed; T
mb
=25°C; see Figure 3 -240A
P
tot
total power dissipation T
mb
=25°C; see Figure 2 -300W
T
stg
storage temperature -55 175 °C
T
j
junction temperature -55 175 °C
Source-drain diode
I
S
source current T
mb
=25°C - 75 A
I
SM
peak source current t
p
≤ 10 µs; pulsed; T
mb
=25°C - 240 A
Avalanche ruggedness
E
DS(AL)S
non-repetitive
drain-source avalanche
energy
V
GS
=10V; T
j(init)
=25°C; I
D
=36A; V
sup
≤ 50 V;
unclamped; t
p
= 0.11 ms; R
GS
=50Ω
-320mJ