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PSMN2R0-30YLE

N-channel 30 V 2 mΩ logic level MOSFET in LFPAK

12 October 2012 Product data sheet

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1. Product profile

1.1 General description

Logic level N-channel MOSFET in LFPAK package qualified to 175 °C. This product

is designed and qualified for use in a wide range of industrial, communications and

domestic equipment.

1.2 Features and benefits

•

Enhanced forward biased safe operating area for superior linear mode operation

•

Very low Rdson for low conduction losses

1.3 Applications

•

Electronic fuse

•

Hot swap

•

Load switch

•

Soft start

1.4 Quick reference data

Table 1. Quick reference data

Symbol Parameter Conditions Min Typ Max Unit

drain-source voltage T

≥ 25 °C; T

≤ 175 °C - - 30 V

drain current T

= 25 °C; V

= 10 V; Fig. 1 [1] - - 100 A

tot

total power dissipation T

= 25 °C; Fig. 2 - - 272 W

Static characteristics

= 10 V; I

= 25 A; T

= 25 °C;

Fig. 12

- 1.7 2 mΩR

DSon

drain-source on-state

resistance

= 4.5 V; I

= 25 A; T

= 25 °C;

Fig. 12

- 3 3.5 mΩ

Dynamic characteristics

gate-drain charge V

= 4.5 V; I

= 25 A; V

= 15 V;

Fig. 14; Fig. 15

- 13.8 - nC

G(tot)

total gate charge V

= 10 V; I

= 25 A; V

= 15 V;

Fig. 14; Fig. 15

- 87 - nC

Summary of content (13 pages)

PAGE 1
PSMN2R0-30YLE N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 12 October 2012 Product data sheet 1. Product profile 1.1 General description Logic level N-channel MOSFET in LFPAK package qualified to 175 °C. This product is designed and qualified for use in a wide range of industrial, communications and domestic equipment. 1.2 Features and benefits • Enhanced forward biased safe operating area for superior linear mode operation • Very low Rdson for low conduction losses 1.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK Symbol Parameter Conditions Min Typ Max Unit VGS = 10 V; Tj(init) = 25 °C; ID = 100 A; - - 370 mJ Avalanche ruggedness EDS(AL)S non-repetitive drainsource avalanche energy [1] Vsup ≤ 30 V; unclamped; RGS = 50 Ω; Fig. 3 Capped at 100A due to package 2. Pinning information Table 2.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK Symbol Parameter Conditions ID drain current VGS = 10 V; Tmb = 100 °C; Fig. 1 VGS = 10 V; Tmb = 25 °C; Fig. 1 Min Max Unit [1] - 100 A [1] - 100 A IDM peak drain current pulsed; tp ≤ 10 µs; Tmb = 25 °C; Fig. 4 - 1084 A Ptot total power dissipation Tmb = 25 °C; Fig.
PAGE 4
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 003aaj896 103 IAL(A) 102 (1) (2) 10 1 10-3 Fig. 3. 10-2 10-1 1 tAL(ms) 10 Single pulse avalanche rating; avalanche current as a function of avalanche time 003aah012 104 ID (A) 103 Limit RDSon = V DS / ID tp =10 µ s 102 100 µ s 1 ms 10 DC 10 ms 100 ms 1 10-1 Fig. 4. 1 10 102 VDS (V) Safe operating area; continuous and peak drain currents as a function of drain-source voltage 6.
PAGE 5
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 003aag993 1 Z th(j-mb) (K/W) 10 δ = 0.5 -1 0.2 0.1 0.05 P 0.02 10-2 tp T δ= single shot tp 10 -3 10-6 Fig. 5. 10-5 10-4 10-3 10-2 t T 10-1 1 tp (s) Transient thermal impedance from junction to mounting base as a function of pulse duration 7. Characteristics Table 7.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK Symbol Parameter Conditions Min Typ Max Unit RG internal gate resistance (AC) f = 1 MHz 0.3 0.6 1.2 Ω ID = 25 A; VDS = 15 V; VGS = 10 V; - 87 - nC - 41 - nC ID = 0 A; VDS = 0 V; VGS = 10 V - 79 - nC gate-source charge ID = 25 A; VDS = 15 V; VGS = 4.5 V; - 13.3 - nC QGS(th) pre-threshold gatesource charge Fig. 14; Fig. 15 - 8.1 - nC QGS(th-pl) post-threshold gatesource charge - 5.
PAGE 7
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 003aah014 100 10 ID (A) 003aah015 8 VGS (V) = 3.5 4.5 RDSon (mΩ ) 80 6 60 4 3 40 2.8 20 2 2.6 2.4 0 Fig. 6. 0 0.5 1 1.5 0 2 VDS(V) Output characteristics; drain current as a Fig. 7.
PAGE 8
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 003aaj515 3 003aaj514 10-1 ID (A) VGS(th) (V) 10-2 max 2 typ min 10-3 max typ 10-4 min 1 10-5 0 -60 0 60 120 Tj (°C) 10-6 180 Fig. 10. Gate-source threshold voltage as a function of junction temperature 30 1 2 V GS (V) 3 Fig. 11. Sub-threshold drain current as a function of gate-source voltage 003aah020 003aag820 2 VGS (V) = 3 2.8 0 a RDSon (mΩ ) 1.5 20 1 10 3.5 0.5 4.
PAGE 9
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 003aah022 10 VDS VGS (V) ID 8 VGS(pl) 24 V 6 VGS(th) VGS VDS = 15V 4 QGS1 QGS2 QGS 6V QGD 2 QG(tot) 003aaa508 0 Fig. 14. Gate charge waveform definitions 0 20 40 60 80 100 QG (nC) Fig. 15.
PAGE 10
PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 8. Package outline Plastic single-ended surface-mounted package (LFPAK; Power-SO8); 4 leads E A2 A SOT669 C c2 b2 E1 b3 L1 mounting base b4 D1 D H L2 1 2 3 e 4 w M A b X c 1/2 e A (A 3) A1 C θ L detail X 0 2.5 y C 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 A2 A3 b b2 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 mm b3 b4 2.2 2.0 0.9 0.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 9.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.
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PSMN2R0-30YLE NXP Semiconductors N-channel 30 V 2 mΩ logic level MOSFET in LFPAK 10. Contents 1 1.1 1.2 1.3 1.4 Product profile ....................................................... 1 General description .............................................. 1 Features and benefits ...........................................1 Applications .......................................................... 1 Quick reference data ............................................ 1 2 Pinning information ....................