Datasheet

Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor 133
the intermediate conversion data is lost. In 8-bit mode, there is no interlocking with ADCRH. If the MODE
bits are changed, any data in ADCRL becomes invalid.
9.3.5 Compare Value High Register (ADCCVH)
In 10-bit mode, the ADCCVH register holds the upper two bits of the 10-bit compare value (ADCV[9:8]).
When the compare function is enabled, these bits are compared to the upper two bits of the result following
a conversion in 10-bit mode.
In 8-bit operation, ADCCVH is not used during compare.
9.3.6 Compare Value Low Register (ADCCVL)
The ADCCVL register holds the lower eight bits of the 10-bit compare value or all eight bits of the 8-bit
compare value. When the compare function is enabled, bits ADCV[7:0] are compared to the lower eight
bits of the result following a conversion in 10-bit or 8-bit mode.
9.3.7 Configuration Register (ADCCFG)
ADCCFG selects the mode of operation, clock source, clock divide, and configures for low power and long
sample time.
7 654 3 210
R ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-6. Data Result Low Register (ADCRL)
7654 3 210
R0000
ADCV9 ADCV8
W
Reset: 0 0 0 0 0 0 0 0
= Unimplemented or Reserved
Figure 9-7. Compare Value High Register (ADCCVH)
7 654 3 210
R
ADCV7 ADCV6 ADCV5 ADCV4 ADCV3 ADCV2 ADCV1 ADCV0
W
Reset: 0 0 0 0 0 0 0 0
Figure 9-8. Compare Value Low Register (ADCCVL)