Datasheet

MC9S08SG32 Data Sheet, Rev. 8
18 Freescale Semiconductor
Section Number Title Page
15.5 Functional Description .................................................................................................................. 236
15.5.1 SPI Clock Formats.......................................................................................................... 236
15.5.2 SPI Interrupts .................................................................................................................. 239
15.5.3 Mode Fault Detection ..................................................................................................... 239
Chapter 16
Timer Pulse-Width Modulator (S08TPMV3)
16.1 Introduction ................................................................................................................................... 241
16.1.1 TPM Configuration Information..................................................................................... 241
16.1.2 TPM Pin Repositioning .................................................................................................. 241
16.1.3 Features........................................................................................................................... 243
16.1.4 Modes of Operation ........................................................................................................ 243
16.1.5 Block Diagram................................................................................................................ 244
16.2 Signal Description......................................................................................................................... 246
16.2.1 Detailed Signal Descriptions........................................................................................... 246
16.3 Register Definition ........................................................................................................................ 250
16.3.1 TPM Status and Control Register (TPMxSC) ................................................................ 250
16.3.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL).................................................... 251
16.3.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL).................................... 252
16.3.4 TPM Channel n Status and Control Register (TPMxCnSC) .......................................... 253
16.3.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) .......................................... 254
16.4 Functional Description .................................................................................................................. 256
16.4.1 Counter............................................................................................................................ 256
16.4.2 Channel Mode Selection................................................................................................. 258
16.5 Reset Overview ............................................................................................................................. 261
16.5.1 General............................................................................................................................ 261
16.5.2 Description of Reset Operation....................................................................................... 261
16.6 Interrupts ....................................................................................................................................... 261
16.6.1 General............................................................................................................................ 261
16.6.2 Description of Interrupt Operation.................................................................................. 262
16.7 The Differences from TPM v2 to TPM v3.................................................................................... 263
Chapter 17
Development Support
17.1 Introduction ................................................................................................................................... 269
17.1.1 Forcing Active Background............................................................................................ 269
17.1.2 Features........................................................................................................................... 270
17.2 Background Debug Controller (BDC) .......................................................................................... 270
17.2.1 BKGD Pin Description ................................................................................................... 271
17.2.2 Communication Details .................................................................................................. 272
17.2.3 BDC Commands............................................................................................................. 276
17.2.4 BDC Hardware Breakpoint............................................................................................. 278