Datasheet

Chapter 16 Timer/PWM Module (S08TPMV3)

MC9S08SG32 Data Sheet, Rev. 8

248 Freescale Semiconductor

When a channel is conﬁgured for edge-aligned PWM (CPWMS=0, MSnB=1 and ELSnB:ELSnA not =

0:0), the data direction is overridden, the TPMxCHn pin is forced to be an output controlled by the TPM,

and ELSnA controls the polarity of the PWM output signal on the pin. When ELSnB:ELSnA=1:0, the

TPMxCHn pin is forced high at the start of each new period (TPMxCNT=0x0000), and the pin is forced

low when the channel value register matches the timer counter. When ELSnA=1, the TPMxCHn pin is

forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the

channel value register matches the timer counter.

Figure 16-3. High-True Pulse of an Edge-Aligned PWM

Figure 16-4. Low-True Pulse of an Edge-Aligned PWM

CHnF BIT

TOF BIT

0...

345

780 12...

TPMxMODH:TPMxMODL = 0x0008

TPMxCnVH:TPMxCnVL = 0x0005

TPMxCNTH:TPMxCNTL

TPMxCHn