Datasheet

Appendix A Electrical Characteristics
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor 295
A.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the human body
model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions
Model Description Symbol Value Unit
Human
Body
Series resistance R1 1500
Ω
Storage capacitance C 100 pF
Number of pulses per pin — 3 —
Latch-up
Minimum input voltage limit — – 2.5 V
Maximum input voltage limit — 7.5 V
Table A-5. ESD and Latch-Up Protection Characteristics
No.
Rating
1
1
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
Symbol Min Max Unit
1 Human body model (HBM)
V
HBM
± 2000 — V
2 Charge device model (CDM)
V
CDM
± 500 — V
3
Latch-up current at T
A
= 125°CI
LAT
± 100 — mA