Datasheet

Chapter 2 Pins and Connections
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor 31
19 15 11 PTB1 PIB1 TxD ADP5
20 16 12 PTB0 PIB0 RxD ADP4
21 — — PTA7 TPM2CH1
6
22 — — PTA6 TPM2CH0
6
23 17 13 PTA3 PIA3 SCL
3
ADP3
24 18 14 PTA2 PIA2 SDA
3
ACMPO ADP2
25 19 15 PTA1 PIA1 TPM2CH0
6
ADP1
7
ACMP-
7
26 20 16 PTA0 PIA0 TPM1CH0
4
TCLK ADP0
7
ACMP+
7
27 — — PTC7 ADP15
28 — — PTC6 ADP14
1
The 20-pin package is not available for the high-temperature rated devices.
2
Pin is open drain with an internal pullup that is always enabled. Pin does not contain a clamp diode to V
DD
and should not be driven above V
DD
. The voltage measured on the internally pulled up RESET will not be
pulled to V
DD
. The internal gates connected to this pin are pulled to V
DD
.
3
IIC pins can be repositioned using IICPS in SOPT2, default reset locations are PTA2, PTA3.
4
TPM1CHx pins can be repositioned using T1CHxPS bits in SOPT2, default reset locations are PTA0, PTB5.
5
This port pin is part of the ganged output feature. When pin is enabled for ganged output, it will have priority
over all digital modules. The output data, drive strength and slew-rate control of this port pin will follow the
configuration for the PTC0 pin, even in 16-pin packages where PTC0 doesn’t bond out.
6
TPM2CHx pins can be repositioned using T2CHxPS bits in SOPT2, default reset locations are PTA1, PTB4.
7
If ACMP and ADC are both enabled, both will have access to the pin.
Table 2-1. Pin Availability by Package Pin-Count (continued)
Pin Number
Priority
28-pin 20-pin
1
16-pin Port Pin Alt 1 Alt 2 Alt 3 Alt 4 Alt 5
Lowest
Highest