Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08SG32 Data Sheet, Rev. 8
Freescale Semiconductor 73
5.7.6 System Power Management Status and Control 1 Register
(SPMSC1)
This high page register contains status and control bits to support the low-voltage detect function, and to
enable the bandgap voltage reference for use by the ADC and ACMP modules. This register should be
written during the user’s reset initialization program to set the desired controls even if the desired settings
are the same as the reset settings.
Figure 5-8. System Power Management Status and Control 1 Register (SPMSC1)
76543210
R LVWF
1
1
LVWF will be set in the case when V
Supply
transitions below the trip point or after reset and V
Supply
is already below V
LVW
0
LVWIE LVDRE
2
2
This bit can be written only one time after reset. Additional writes are ignored.
LVDSE
2
LVDE
2
0
BGBE
W LVWACK
Reset: 00011100
= Unimplemented or Reserved
Table 5-9. SPMSC1 Register Field Descriptions
Field Description
7
LVWF
Low-Voltage Warning Flag — The LVWF bit indicates the low voltage warning status.
0 Low voltage warning is not present.
1 Low voltage warning is present or was present.
6
LVWACK
Low-Voltage Warning Acknowledge — The LVWF bit indicates the low voltage warning status.Writing a 1 to
LVWACK clears LVWF to a 0 if a low voltage warning is not present.
5
LVWIE
Low-Voltage Warning Interrupt Enable — This bit enables hardware interrupt requests for LVWF.
0 Hardware interrupt disabled (use polling).
1 Request a hardware interrupt when LVWF = 1.
4
LVDRE
Low-Voltage Detect Reset Enable — This write-once bit enables LVD events to generate a hardware reset
(provided LVDE = 1).
0 LVD events do not generate hardware resets.
1 Force an MCU reset when an enabled low-voltage detect event occurs.
3
LVDSE
Low-Voltage Detect Stop Enable — Provided LVDE = 1, this write-once bit determines whether the low-voltage
detect function operates when the MCU is in stop mode.
0 Low-voltage detect disabled during stop mode.
1 Low-voltage detect enabled during stop mode.
2
LVDE
Low-Voltage Detect Enable — This write-once bit enables low-voltage detect logic and qualifies the operation
of other bits in this register.
0 LVD logic disabled.
1 LVD logic enabled.
0
BGBE
Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the
ADC and ACMP modules.
0 Bandgap buffer disabled.
1 Bandgap buffer enabled.