Datasheet

Chapter 16 Timer Pulse-Width Modulator (S08TPMV3)

MC9S08SG8 MCU Series Data Sheet, Rev. 8

Freescale Semiconductor 239

• In edge- or center- aligned modes, the Channel Value register (TPMxCnV) registers only update

when the timer changes from TPMMOD-1 to TPMMOD, or in the case of a free running timer

from 0xFFFE to 0xFFFF.

• Also, when configuring the TPM modules, it is best to write to TPMxSC before TPMxCnV as a

write to TPMxSC resets the coherency mechanism on the TPMxCnV registers.

Table 16-3. Migrating to TPMV3 Considerations

When... Action / Best Practice

Writing to the Channel Value Register (TPMxCnV)

Timer must be in Input Capture mode.

Updating the Channel Value Register (TPMxCnV)

Only occurs when the timer changes from

TPMMOD-1 to TPMMOD (or in the case of a free

running timer, from 0xFFFE to 0xFFFF).

Reseting the coherency mechanism for the

Channel Value Register (TPMxCnV) register...

Write to TPMxSC.

Configuring the TPM modules... Write first to TPMxSC and then to TPMxCnV