Datasheet

Appendix A Electrical Characteristics
MC9S08SG8 MCU Series Data Sheet, Rev. 8
Freescale Semiconductor 299
A.9 Internal Clock Source (ICS) Characteristics
Table A-9. ICS Frequency Specifications (Temperature Range = –40 to 125C Ambient)
Nu
m
C Rating Symbol Min Typ Max Unit
Temp Rated
1
1
Electrical characteristics only apply to the temperature rated devices marked with x.
Standard
AEC
Grade 0
1P
Internal reference frequency - factory
trimmed
at V
DD
= 5 V
f
int_ft
— 31.25 — kHz x x
2P
Internal reference frequency -
untrimmed
2
2
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
f
int_ut
25 36 41.66 kHz x x
3P
Internal reference frequency - user
trimmed
f
int_t
31.25 — 39.0625 kHz x x
4 D Internal reference startup time
t
irefst
— 55 100 sx x
5—
DCO output frequency range -
untrimmed
1

value provided for reference: f
dco_ut
=
1024  f
int_ut
f
dco_ut
25.6 36.86 42.66 MHz x x
6D
DCO output frequency range -
trimmed
f
dco_t
32 — 40 MHz x
32 — 36 MHz x
7D
Resolution of trimmed DCO output
frequency at fixed voltage and
temperature (using FTRIM)
f
dco_res_t
— 0.1 0.2
%f
dco
xx
8D
Resolution of trimmed DCO output
frequency at fixed voltage and
temperature (not using FTRIM)
f
dco_res_t
— 0.2 0.4
%f
dco
xx
9P
Total deviation from actual trimmed
DCO output frequency over voltage
and temperature
f
dco_t
—
+ 0.5
– 1.0
1.5
%f
dco
x
—
+ 0.5
– 1.0
3
%f
dco
x
10 D
Total deviation of trimmed DCO output
frequency over fixed voltage and
temperature range of 0
C to 70 C
f
dco_t
— 0.5 1
%f
dco
xx
11 D
FLL acquisition time
3
3
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or
changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used
as the reference, this specification assumes it is already running.
t
acquire
1ms x x
12 D
DCO output clock long term jitter (over
2mS interval)
4
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via V
DD
and V
SS
and variation in crystal oscillator frequency increase the C
Jitter
percentage for a given interval.
C
Jitter
—0.020.2
%f
dco
xx