Datasheet

Appendix A Electrical Characteristics
MC9S08SG8 MCU Series Data Sheet, Rev. 8
308 Freescale Semiconductor
A.12.3 SPI
Table A-15 and Figure A-14 through Figure A-17 describe the timing requirements for the SPI system.
Table A-15. SPI Electrical Characteristic
Num
1
1
Refer to Figure A-14 through Figure A-17.
C Rating
2
2
All timing is shown with respect to 20% V
DD
and 70% V
DD
, unless noted; 100 pF load on all SPI pins. All timing assumes slew
rate control disabled and high drive strength enabled for SPI output pins.
Symbol Min Max Unit
Temp Rated
3
3
Electrical characteristics only apply to the temperature rated devices marked with x.
Standard
AEC Grade
0
1D
Cycle time
Master
Slave
t
SCK
t
SCK
2
4
2048
—
t
cyc
t
cyc
xx
2D
Enable lead time
Master
Slave
t
Lead
t
Lead
—
1/2
1/2
—
t
SCK
t
SCK
xx
3D
Enable lag time
Master
Slave
t
Lag
t
Lag
—
1/2
1/2
—
t
SCK
t
SCK
xx
4D
Clock (SPSCK) high time
Master and Slave
t
SCKH
1/2 t
SCK
– 25 — ns
xx
5D
Clock (SPSCK) low time
Master and Slave
t
SCKL
1/2 t
SCK
– 25 — ns
xx
6D
Data setup time (inputs)
Master
Slave
t
SI(M)
t
SI(S)
30
30
—
—
ns
ns
xx
7D
Data hold time (inputs)
Master
Slave
t
HI(M)
t
HI(S)
30
30
—
—
ns
ns
xx
8 D Access time, slave
4
4
Time to data active from high-impedance state.
t
A
040ns
xx
9 D Disable time, slave
5
5
Hold time to high-impedance state.
t
dis
—40ns
xx
10 D
Data setup time (outputs)
Master
Slave
t
SO
t
SO
25
25
—
—
ns
ns
xx
11 D
Data hold time (outputs)
Master
Slave
t
HO
t
HO
–10
–10
—
—
ns
ns
xx
12 D
Operating frequency
Master
Slave
f
op
f
op
f
Bus
/2048
dc
5
6
f
Bus
/4
6
Maximum baud rate must be limited to 5 MHz due to input filter characteristics.
MHz
xx