Datasheet

Chapter 5 Resets, Interrupts, and General System Control
MC9S08SG8 MCU Series Data Sheet, Rev. 8
74 Freescale Semiconductor
5.7.7 System Power Management Status and Control 2 Register
(SPMSC2)
This register is used to report the status of the low voltage warning function, and to configure the stop
mode behavior of the MCU.
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
76543 210
R0 0
LVDV
1
1
This bit can be written only one time after power-on reset. Additional writes are ignored.
LVWV
PPDF 0 0
PPDC
2
2
This bit can be written only one time after reset. Additional writes are ignored.
W PPDACK
Power-on Reset:00000 000
LVD Reset:00uu0 000
Any other Reset: 0 0 u u 0 0 0 0
= Unimplemented or Reserved u = Unaffected by reset
Table 5-10. SPMSC2 Register Field Descriptions
Field Description
5
LVDV
Low-Voltage Detect Voltage Select — This write-once bit selects the low voltage detect (LVD) trip point setting.
It also selects the warning voltage range. See Table 5-11.
4
LVWV
Low-Voltage Warning Voltage Select — This bit selects the low voltage warning (LVW) trip point voltage. See
Table 5-11.
3
PPDF
Partial Power Down Flag — This read-only status bit indicates that the MCU has recovered from stop2 mode.
0 MCU has not recovered from stop2 mode.
1 MCU recovered from stop2 mode.
2
PPDACK
Partial Power Down Acknowledge — Writing a 1 to PPDACK clears the PPDF bit
0
PPDC
Partial Power Down Control — This write-once bit controls whether stop2 or stop3 mode is selected.
0 Stop3 mode enabled.
1 Stop2, partial power down, mode enabled.
Table 5-11. LVD and LVW trip point typical values
1
1
See Electrical Characteristics appendix for minimum and maximum values.
LVDV:LVWV LVW Trip Point LVD Trip Point
0:0 V
LVW 0
= 2.74 V V
LVD0
= 2.56 V
0:1 V
LVW 1
= 2.92 V
1:0 V
LVW 2
= 4.3 V V
LVD 1
= 4.0 V
1:1 V
LVW 3
= 4.6 V